知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.014 seconds)

    METHOD AND SYSTEM FOR VERIFYING THE DESIGN OF AN INTEGRATED CIRCUIT HAVING MULTIPLE TIERS
    2.
    发明申请
    METHOD AND SYSTEM FOR VERIFYING THE DESIGN OF AN INTEGRATED CIRCUIT HAVING MULTIPLE TIERS 有权
    用于验证具有多个层次的集成电路设计的方法和系统

    公开(公告)号：US20150269303A1

    公开(公告)日：2015-09-24

    申请号：US14219029

    申请日：2014-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Hsien TSAI ,  Chi-Ting HUANG ,  Cheng-Hung YEH ,  Hsien-Hsin Sean LEE

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/82

    Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

    Abstract translation: 一种用于验证具有多个层的IC的设计的方法包括进行布局与示意图（“LVS”）检查以分离多个设计布局中的多个设备，其中每个设计布局对应于具有 各自的设备。 使用计算设备在彼此的不同层中的一个设备之间生成多个相邻层连接。 执行每个层的第一RC提取以计算相应设计布局的多个设备中的每一个之间的耦合。 执行每个相邻层连接的第二RC提取。

    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
    4.
    发明申请
    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE 审中-公开

    公开(公告)号：US20200258846A1

    公开(公告)日：2020-08-13

    申请号：US16863934

    申请日：2020-04-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu LEE ,  Chin-Chou LIU ,  Cheng-Hung YEH ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Yi-Kan CHENG ,  Ka Fai CHANG

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

    SYSTEMS AND METHODS FOR DETERMINING EFFECTIVE CAPACITANCE TO FACILITATE A TIMING ANALYSIS
    6.
    发明申请
    SYSTEMS AND METHODS FOR DETERMINING EFFECTIVE CAPACITANCE TO FACILITATE A TIMING ANALYSIS 审中-公开
    用于确定有效电容以促进时序分析的系统和方法

    公开(公告)号：US20150154343A1

    公开(公告)日：2015-06-04

    申请号：US14562793

    申请日：2014-12-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang YEH ,  Cheng-Hung YEH ,  Chi-Ting HUANG

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036

    Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

    Abstract translation: 一种用于定时分析的方法包括使用该处理器来确定至少第一级间通路（ILV）和第二ILV或器件之间的耦合的阻抗曲线，作为至少不同频率值的函数。 阻抗曲线包括对应于各个频率值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 为每个相应的频率值提供至少一个表，其具有相应的阻抗值和相应的有效电容值。 使用填充表并基于确定的有效电容值来进行ILV电路的设计布局的RC提取。

Patent Agency Ranking