公开(公告)号：US20190245031A1

公开(公告)日：2019-08-08

申请号：US16387844

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108 ,  H01L21/321

CPC classification number: H01L28/91 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/764 ,  H01L23/562 ,  H01L27/016 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/87 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20200066922A1

公开(公告)日：2020-02-27

申请号：US16113028

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Jing-Hwang Yang ,  Ting-Chen Hsu ,  Felix Ying-Kit Tsui ,  Yen-Wen Chen

IPC: H01L29/94 ,  H01L49/02 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high κ dielectric material. By using a high κ material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

公开(公告)号：US10509008B2

公开(公告)日：2019-12-17

申请号：US14700133

申请日：2015-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Yi-Shao Liu ,  Tung-Tsun Chen ,  Chan-Ching Lin ,  Jui-Cheng Huang ,  Felix Ying-Kit Tsui ,  Jing-Hwang Yang

IPC: G01N27/414

Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

公开(公告)号：US12272725B2

公开(公告)日：2025-04-08

申请号：US18341498

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/01 ,  H01L29/66 ,  H01L29/94 ,  H10B12/00 ,  H01L27/08

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US10693019B2

公开(公告)日：2020-06-23

申请号：US16113028

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Jing-Hwang Yang ,  Ting-Chen Hsu ,  Felix Ying-Kit Tsui ,  Yen-Wen Chen

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/94 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high κ dielectric material. By using a high κ material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

公开(公告)号：US10276651B2

公开(公告)日：2019-04-30

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/306

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20230361166A1

公开(公告)日：2023-11-09

申请号：US18341498

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L29/94 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/764 ,  H01L21/321 ,  H01L27/01 ,  H01L21/3213 ,  H01L23/00 ,  H01L21/027 ,  H01L21/3205 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L28/91 ,  H10B12/37 ,  H01L21/31111 ,  H01L28/87 ,  H01L21/31053 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/3212 ,  H01L27/016 ,  H01L21/32133 ,  H10B12/0387 ,  H01L29/945 ,  H01L28/92 ,  H01L23/562 ,  H01L21/0274 ,  H01L21/32055 ,  H01L29/66181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2924/19105 ,  H01L27/0805 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/13101 ,  H01L2924/1304 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2224/48227 ,  H01L2924/19011 ,  H01L2924/19103 ,  H01L2224/73204 ,  H01L2224/48091 ,  H01L2924/13091 ,  H01L2924/1305 ,  H01L2924/00014 ,  H01L2224/32145

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US11688762B2

公开(公告)日：2023-06-27

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H10B12/00 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L27/08

CPC classification number: H01L28/91 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/764 ,  H01L23/562 ,  H01L27/016 ,  H01L28/87 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H10B12/0387 ,  H10B12/37 ,  H01L27/0805 ,  H01L2224/13101 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1305 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20190074349A1

公开(公告)日：2019-03-07

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/108 ,  H01L23/00

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US11828722B2

公开(公告)日：2023-11-28

申请号：US16716196

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Yi-Shao Liu ,  Tung-Tsun Chen ,  Chan-Ching Lin ,  Jui-Cheng Huang ,  Felix Ying-Kit Tsui ,  Jing-Hwang Yang

IPC: G01N27/414

CPC classification number: G01N27/4145

Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.