公开(公告)号：US12272725B2

公开(公告)日：2025-04-08

申请号：US18341498

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/01 ,  H01L29/66 ,  H01L29/94 ,  H10B12/00 ,  H01L27/08

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US12085761B2

公开(公告)日：2024-09-10

申请号：US18201110

申请日：2023-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tsung Shih ,  Chewn-Pu Jou ,  Stefan Rusu ,  Felix Ying-Kit Tsui ,  Lan-Chou Cho

IPC: G02B6/34 ,  G02B6/30

CPC classification number: G02B6/34 ,  G02B6/305

Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.

公开(公告)号：US20210280592A1

公开(公告)日：2021-09-09

申请号：US17068924

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and comprises source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and comprises source/drain regions disposed on the opposite sides of the floating gate.

公开(公告)号：US10693019B2

公开(公告)日：2020-06-23

申请号：US16113028

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Jing-Hwang Yang ,  Ting-Chen Hsu ,  Felix Ying-Kit Tsui ,  Yen-Wen Chen

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/94 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high κ dielectric material. By using a high κ material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

公开(公告)号：US10276651B2

公开(公告)日：2019-04-30

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/306

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US09601411B2

公开(公告)日：2017-03-21

申请号：US14963235

申请日：2015-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Hsiao-Chin Tuan ,  Shih-Fen Huang ,  Hsin-Li Cheng ,  Felix Ying-Kit Tsui

IPC: H01L29/74 ,  H01L31/111 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

公开(公告)号：US11828722B2

公开(公告)日：2023-11-28

申请号：US16716196

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Yi-Shao Liu ,  Tung-Tsun Chen ,  Chan-Ching Lin ,  Jui-Cheng Huang ,  Felix Ying-Kit Tsui ,  Jing-Hwang Yang

IPC: G01N27/414

CPC classification number: G01N27/4145

Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

公开(公告)号：US11693186B2

公开(公告)日：2023-07-04

申请号：US17220724

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tsung Shih ,  Chewn-Pu Jou ,  Stefan Rusu ,  Felix Ying-Kit Tsui ,  Lan-Chou Cho

IPC: G02B6/34 ,  G02B6/30

CPC classification number: G02B6/34 ,  G02B6/305

Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a described apparatus includes: a planar layer; a grating region comprising an array of scattering elements arranged in the planar layer to form a two-dimensional grating; a first taper structure formed in the planar layer connecting a first side of the grating region to a first waveguide, wherein a shape of the first taper structure is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region in the planar layer; and a second taper structure formed in the planar layer connecting a second side of the grating region to a second waveguide, wherein a shape of the second taper structure is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region in the planar layer, wherein the first side and the second side are substantially perpendicular to each other.

公开(公告)号：US20210280591A1

公开(公告)日：2021-09-09

申请号：US16807537

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: H01L27/11524 ,  H01L49/02 ,  H01L29/423 ,  G11C16/10 ,  G11C16/26 ,  H01L29/08 ,  H01L21/28 ,  H01L29/66 ,  G11C16/04 ,  H01L29/788 ,  G11C16/14

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

公开(公告)号：US20210104598A1

公开(公告)日：2021-04-08

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.