公开(公告)号：US20220301964A1

公开(公告)日：2022-09-22

申请号：US17834938

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

公开(公告)号：US09190347B2

公开(公告)日：2015-11-17

申请号：US13967165

申请日：2013-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Abstract translation: 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。

公开(公告)号：US20240355795A1

公开(公告)日：2024-10-24

申请号：US18659033

申请日：2024-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/24 ,  H01L25/18 ,  H01L25/0652 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/3511

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US12046588B2

公开(公告)日：2024-07-23

申请号：US17672719

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/24 ,  H01L25/18 ,  H01L25/0652 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/3511

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US20230369152A1

公开(公告)日：2023-11-16

申请号：US18356243

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/565 ,  H01L24/03 ,  H01L23/3171 ,  H01L24/09 ,  H01L2924/1811 ,  H01L2224/02379 ,  H01L25/0756

Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.

公开(公告)号：US11437361B2

公开(公告)日：2022-09-06

申请号：US16569078

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jen Lai ,  Lin Chung-Yi ,  Hsi-Kuei Cheng ,  Chen-Shien Chen ,  Kuo-Chio Liu

IPC: H01L25/00 ,  H01L25/10 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L21/683 ,  H01L21/56

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

公开(公告)号：US12051634B2

公开(公告)日：2024-07-30

申请号：US18356243

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

CPC classification number: H01L23/3121 ,  H01L21/565 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/09 ,  H01L24/23 ,  H01L24/25 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/02379 ,  H01L2224/2105 ,  H01L2224/2205 ,  H01L2224/23 ,  H01L2224/2401 ,  H01L2224/2405 ,  H01L2224/2505 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2225/1058 ,  H01L2924/1811

Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.

公开(公告)号：US10276548B2

公开(公告)日：2019-04-30

申请号：US15669563

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Hsiu-Jen Lin ,  Ming-Chih Yew ,  Ming-Da Cheng ,  Yi-Jen Lai ,  Yu-Tse Su ,  Sey-Ping Sun ,  Yang-Che Chen

IPC: H01L23/02 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

公开(公告)号：US20130328215A1

公开(公告)日：2013-12-12

申请号：US13967165

申请日：2013-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Abstract translation: 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。

公开(公告)号：US10651111B2

公开(公告)日：2020-05-12

申请号：US15889450

申请日：2018-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： You-Hua Chou ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Perre Kao

IPC: H01L23/473 ,  H01L23/488 ,  H01L23/48 ,  H01L23/36 ,  H01L25/065 ,  H01L23/00 ,  H01L23/42 ,  H01L23/367

Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.