公开(公告)号：US20240379558A1

公开(公告)日：2024-11-14

申请号：US18777557

申请日：2024-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/768

Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

公开(公告)号：US20240355803A1

公开(公告)日：2024-10-24

申请号：US18757882

申请日：2024-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Han-Tang HUNG ,  Ming-Han LEE ,  Shau-Lin SHUE ,  Shin-Yi YANG

IPC: H01L25/18 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/485 ,  H01L23/58 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/485 ,  H01L23/585 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16225

Abstract: Embodiments of the present disclosure provide a method for manufacturing a semiconductor package. The method includes providing a first integrated circuit (IC) die, wherein the first IC die has a first back-end-of-the-line (BEOL) structure. The method includes providing a first guard ring, wherein the first guard ring is disposed to encircle conductive features of the first BEOL. The method includes providing a second IC die, wherein the second IC die has a second BEOL structure, providing a second guard ring, wherein the second guard ring is disposed to encircle conductive features of the second BEOL. The method further includes providing an integrated BEOL structure, wherein a first side of the integrated BEOL structure is in direct contact with the first BEOL structure and the second BEOL structure.

公开(公告)号：US20240087990A1

公开(公告)日：2024-03-14

申请号：US18516971

申请日：2023-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/482 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/4822 ,  H01L23/481 ,  H01L23/5286 ,  H01L25/0652 ,  H01L25/50 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line. The method also includes forming a first interconnect structure on a first surface of the first integrated circuit die, forming a second interconnect structure on a first surface of the second integrated circuit die, extending a power rail from a second surface of the first integrated circuit die to a first side of a source/drain (S/D) feature, forming one or more power lines through an entire thickness of the first and second integrated circuit dies, respectively, forming a third interconnect structure on the second surface of the first integrated circuit die, and forming a fourth interconnect structure on the second surface of the second integrated circuit die.

公开(公告)号：US20230378148A1

公开(公告)日：2023-11-23

申请号：US18229670

申请日：2023-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Han-Tang HUNG ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L21/78 ,  H01L25/50 ,  H01L2224/73204 ,  H01L2224/16225

Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

公开(公告)号：US20230361079A1

公开(公告)日：2023-11-09

申请号：US18224065

申请日：2023-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/544 ,  H01L23/538 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L24/14 ,  H01L23/544 ,  H01L23/5386 ,  H01L23/14 ,  H01L23/31 ,  H01L23/49811

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

公开(公告)号：US20230378255A1

公开(公告)日：2023-11-23

申请号：US18364291

申请日：2023-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chieh-Han WU ,  Hwei-Jay CHU ,  An-Dih YU ,  Tzu-Hui WEI ,  Cheng-Hsiung TSAI ,  Chung-Ju LEE ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76829 ,  H01L23/5283 ,  H01L21/823481

Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

公开(公告)号：US20230378099A1

公开(公告)日：2023-11-23

申请号：US18230512

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shau-Lin SHUE ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/58 ,  H01L23/522 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L24/97 ,  H01L22/10 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

公开(公告)号：US20230335497A1

公开(公告)日：2023-10-19

申请号：US17720988

申请日：2022-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L23/5226 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76831 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76892

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of intercalated graphene structures and a via. The intercalated graphene structures are disposed over the semiconductor substrate. Each of the intercalated graphene structures includes a plurality of graphene layers each extending substantially parallel to the semiconductor substrate. The via extends into at least a portion of one of the intercalated graphene structures toward the semiconductor substrate, and is in contact with edges of corresponding ones of the graphene layers of the one of the intercalated graphene structures.

公开(公告)号：US20230326857A1

公开(公告)日：2023-10-12

申请号：US17716485

申请日：2022-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Pei LU ,  Shin-Yi YANG ,  Cian-Yu CHEN ,  Yun-Chi CHIANG ,  Ming-Han LEE

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53271 ,  H01L23/5283 ,  H01L23/5226 ,  H01L23/53209 ,  H01L21/76831 ,  H01L23/53295 ,  H01L21/76885 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/7682

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20230207461A1

公开(公告)日：2023-06-29

申请号：US18118372

申请日：2023-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Guanyu LUO ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76843 ,  H01L23/5225 ,  H01L23/53238

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.