公开(公告)号：US12074035B2

公开(公告)日：2024-08-27

申请号：US17742806

申请日：2022-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/3213 ,  H01L29/40

CPC classification number: H01L21/32134 ,  H01L29/401

Abstract: A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.

公开(公告)号：US20230420534A1

公开(公告)日：2023-12-28

申请号：US18153491

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823443

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.

公开(公告)号：US20230420265A1

公开(公告)日：2023-12-28

申请号：US17808175

申请日：2022-06-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tefu Yeh ,  Cheng-Chieh Tu ,  Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/3213

CPC classification number: H01L21/32134

Abstract: Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.

公开(公告)号：US20230386898A1

公开(公告)日：2023-11-30

申请号：US18447134

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Yu-Fang Huang ,  Kuo-Ju Chen ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76805 ,  H01L21/76867 ,  H01L23/5226 ,  H01L21/7685 ,  H01L23/53257

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

公开(公告)号：US20230335443A1

公开(公告)日：2023-10-19

申请号：US18337855

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chi Pan ,  Kuo-Bin Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Yu-Te Su ,  Kuan-Wei Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4966

Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

公开(公告)号：US20230068714A1

公开(公告)日：2023-03-02

申请号：US17460106

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/311

Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

公开(公告)号：US10937656B2

公开(公告)日：2021-03-02

申请号：US16688743

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3213

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US20190006487A1

公开(公告)日：2019-01-03

申请号：US15991761

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

公开(公告)号：US20150206755A1

公开(公告)日：2015-07-23

申请号：US14673024

申请日：2015-03-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chen ,  Shun Wu Lin ,  Chi-Chun Chen ,  Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Matt Yeh ,  Donald Y. Chao ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L21/28105 ,  H01L21/28123 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/401

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract translation: 提供了包括高k栅极电介质的金属栅极结构的图案化方法。 在一个实施方案中，可以使用可溶性硬掩模层来提供掩模元件以对金属栅极进行图案化。 可溶性硬掩模层可以通过水或光致抗蚀剂显影剂从基底上去除。 在一个实施例中，形成包括高k电介质的硬掩模。 在另一个实施例中，保护层形成在光致抗蚀剂图案下面。 保护层可以保护形成在衬底上的一个或多个层与光致抗蚀剂剥离工艺。

公开(公告)号：US12183637B2

公开(公告)日：2024-12-31

申请号：US18337855

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chi Pan ,  Kuo-Bin Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Yu-Te Su ,  Kuan-Wei Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.