公开(公告)号：US20230420538A1

公开(公告)日：2023-12-28

申请号：US17849154

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chi PAN ,  Kuan-Wei Lin ,  Chun-Neng Lin ,  Yu-Shih Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/7851 ,  H01L21/28088 ,  H01L29/66795

Abstract: A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.

公开(公告)号：US20230352306A1

公开(公告)日：2023-11-02

申请号：US18344554

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu Ang Chiang ,  Ming-Hsi Yeh ,  Chun-Neng Lin ,  Jian-Jou Lian ,  Po-Yuan Wang ,  Chieh-Wei Chen

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L21/28132 ,  H01L29/7851 ,  H01L21/28088 ,  H01L29/66795 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/31111

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

公开(公告)号：US20230067300A1

公开(公告)日：2023-03-02

申请号：US17461001

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Yu-Fang Huang ,  Kuo-Ju Chen ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

公开(公告)号：US11380793B2

公开(公告)日：2022-07-05

申请号：US16528031

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US11227940B2

公开(公告)日：2022-01-18

申请号：US16803089

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Chieh-Wei Chen ,  Tzu-Ang Chiang

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.

公开(公告)号：US20210036145A1

公开(公告)日：2021-02-04

申请号：US16528031

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US20220359743A1

公开(公告)日：2022-11-10

申请号：US17868999

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Neng Lin ,  Jian-Jou Lian ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

公开(公告)号：US20210225660A1

公开(公告)日：2021-07-22

申请号：US16746239

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L21/3213 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  C09K13/00

Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

公开(公告)号：US12183823B2

公开(公告)日：2024-12-31

申请号：US17868999

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Neng Lin ,  Jian-Jou Lian ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

公开(公告)号：US12080556B2

公开(公告)日：2024-09-03

申请号：US18344554

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu Ang Chiang ,  Ming-Hsi Yeh ,  Chun-Neng Lin ,  Jian-Jou Lian ,  Po-Yuan Wang ,  Chieh-Wei Chen

IPC: H01L21/28 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28132 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.