公开(公告)号：US20230067300A1

公开(公告)日：2023-03-02

申请号：US17461001

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Yu-Fang Huang ,  Kuo-Ju Chen ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

公开(公告)号：US20230386898A1

公开(公告)日：2023-11-30

申请号：US18447134

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Yu-Fang Huang ,  Kuo-Ju Chen ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76805 ,  H01L21/76867 ,  H01L23/5226 ,  H01L21/7685 ,  H01L23/53257

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

公开(公告)号：US11854870B2

公开(公告)日：2023-12-26

申请号：US17461001

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Chou ,  Yu-Fang Huang ,  Kuo-Ju Chen ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3215

CPC classification number: H01L21/76805 ,  H01L21/7685 ,  H01L21/76867 ,  H01L23/5226 ,  H01L21/3215 ,  H01L23/53257

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

公开(公告)号：US11587875B2

公开(公告)日：2023-02-21

申请号：US16990940

申请日：2020-08-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： U-Ting Chiu ,  Yu-Shih Wang ,  Chun-Cheng Chou ,  Yu-Fang Huang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L23/535 ,  H01L27/11 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.