公开(公告)号：US12094948B2

公开(公告)日：2024-09-17

申请号：US17466501

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Yen-Ju Chen ,  Chun-Chih Cheng ,  Wei-Chen Hsiao

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/78696

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

公开(公告)号：US20230420543A1

公开(公告)日：2023-12-28

申请号：US17809030

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226 ,  H01L21/76814 ,  H01L21/2855 ,  H01L21/28079 ,  H01L29/4958

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

公开(公告)号：US20230420508A1

公开(公告)日：2023-12-28

申请号：US17848406

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei Yun Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/6656 ,  H01L21/823412 ,  H01L21/823468

Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

公开(公告)号：US11854816B2

公开(公告)日：2023-12-26

申请号：US17460085

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Shun Wu Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/306 ,  H01L29/40 ,  H01L21/762 ,  H01L29/417

CPC classification number: H01L21/30604 ,  H01L21/7624 ,  H01L29/401 ,  H01L29/41733

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

公开(公告)号：US20230010952A1

公开(公告)日：2023-01-12

申请号：US17737851

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Yen-Ju Chen ,  Chun-Chih Cheng

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

公开(公告)号：US20230067984A1

公开(公告)日：2023-03-02

申请号：US17460085

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Shun Wu LIN ,  Ming-Hsi Yeh ,  Kuo-Bin HUANG

IPC: H01L21/306 ,  H01L21/762 ,  H01L29/40

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

公开(公告)号：US20240379796A1

公开(公告)日：2024-11-14

申请号：US18781274

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Yen-Ju Chen ,  Chun-Chih Cheng ,  Wei-Chen Hsiao

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

公开(公告)号：US12074035B2

公开(公告)日：2024-08-27

申请号：US17742806

申请日：2022-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/3213 ,  H01L29/40

CPC classification number: H01L21/32134 ,  H01L29/401

Abstract: A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.

公开(公告)号：US20230420534A1

公开(公告)日：2023-12-28

申请号：US18153491

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ling Chung ,  Chun-Chih Cheng ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823443

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.

公开(公告)号：US20220285514A1

公开(公告)日：2022-09-08

申请号：US17466501

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Yen-Ju Chen ,  Chun-Chih Cheng ,  Wei-Chen Hsiao

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.