公开(公告)号：US20230378300A1

公开(公告)日：2023-11-23

申请号：US17864104

申请日：2022-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Chih-Ching WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6653 ,  H01L21/31111

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.

公开(公告)号：US20230052084A1

公开(公告)日：2023-02-16

申请号：US17400446

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Hao CHENG ,  Wei-Yang LEE ,  Tzu-Hua CHIU ,  Wei-Han FAN ,  Po-Yu LIN ,  Chia-Pin LIN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

公开(公告)号：US20220359763A1

公开(公告)日：2022-11-10

申请号：US17313156

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

公开(公告)号：US20240395893A1

公开(公告)日：2024-11-28

申请号：US18791111

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wen-Kai LIN ,  Shih-Chiang CHEN ,  Po-Shao LIN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Yuan-Ching PENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

公开(公告)号：US20240339510A1

公开(公告)日：2024-10-10

申请号：US18745029

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Chia-Pin LIN

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/78696

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of channel structures and a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes an etch stop layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack.

公开(公告)号：US20230017036A1

公开(公告)日：2023-01-19

申请号：US17662038

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Han FAN ,  Chia-Pin LIN ,  Wei-Yang LEE ,  Tzu-Hua CHIU ,  Kuan-Hao CHENG ,  Po Shao LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40

Abstract: A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.

公开(公告)号：US20130228871A1

公开(公告)日：2013-09-05

申请号：US13854251

申请日：2013-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD

Inventor： Yu-Lien HUANG ,  Chia-Pin LIN ,  Sheng-Hsiung WANG ,  Fan-Yi HSU ,  Chun-Liang TAI

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L29/513 ,  H01L29/66545

Abstract: A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.

Abstract translation: 提供了一种在衬底上包括第一栅极结构和在衬底上的第二栅极结构的半导体器件。 半导体器件还包括在第一栅极结构和第二栅极结构之间的衬底上的层间介电层（ILD）层，其中ILD层的顶部部分具有与ILD层的底部不同的蚀刻选择性。

公开(公告)号：US20240363714A1

公开(公告)日：2024-10-31

申请号：US18767188

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Hao CHENG ,  Wei-Yang LEE ,  Tzu-Hua CHIU ,  Wei-Han FAN ,  Po-Yu LIN ,  Chia-Pin LIN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

公开(公告)号：US20240274649A1

公开(公告)日：2024-08-15

申请号：US18644270

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Yuan-Ching PENG

IPC: H01L23/64 ,  H01L27/08 ,  H01L29/06

CPC classification number: H01L28/20 ,  H01L23/647 ,  H01L27/0802 ,  H01L29/0649

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

公开(公告)号：US20230352594A1

公开(公告)日：2023-11-02

申请号：US17732552

申请日：2022-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Sheng LU ,  Chung-Chi WEN ,  Yen-Ting CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Chih-Chiang CHANG ,  Chien-I KUO ,  Yuan-Ching PENG ,  Chih-Ching WANG ,  Wen-Hsing Hsieh ,  Chii-Horng LI ,  Yee-Chia YEO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.