公开(公告)号：US20250070027A1

公开(公告)日：2025-02-27

申请号：US18929920

申请日：2024-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

公开(公告)号：US20240274555A1

公开(公告)日：2024-08-15

申请号：US18313746

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Ming-Hsing Tsai ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Kevin Huang ,  Kuan-Hung Ho

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/0239 ,  H01L2224/0384 ,  H01L2224/05073 ,  H01L2224/05184 ,  H01L2224/05582

Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

公开(公告)号：US11810857B2

公开(公告)日：2023-11-07

申请号：US17001917

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

公开(公告)号：US20220367266A1

公开(公告)日：2022-11-17

申请号：US17382001

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Chih-Yi Chang ,  Wei Hsiang Chan ,  Chih-Chien Chi ,  Chi-Feng Lin ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

公开(公告)号：US11380542B2

公开(公告)日：2022-07-05

申请号：US17013316

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20210272910A1

公开(公告)日：2021-09-02

申请号：US17306784

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun LIU ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US20210265272A1

公开(公告)日：2021-08-26

申请号：US17315579

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

公开(公告)号：US10438846B2

公开(公告)日：2019-10-08

申请号：US15880324

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nai-Hao Yang ,  Hung-Wen Su ,  Kuan-Chia Chen

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/324 ,  H01L21/67 ,  H01L23/532 ,  H01L21/285

Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.

公开(公告)号：US09887073B2

公开(公告)日：2018-02-06

申请号：US14622397

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chien Chi ,  Hung-Wen Su ,  Pei-Hsuan Lee

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/04

CPC classification number: H01J37/3447 ,  C23C14/046 ,  C23C14/35 ,  H01J37/3402

Abstract: A physical vapor deposition system includes a chamber, a cover plate, a pedestal, and a collimator. The cover plate is disposed on the chamber for holding a target. The pedestal is disposed in the chamber for supporting a wafer. The collimator is mounted between the cover plate and the pedestal. The collimator includes a plurality of sidewall sheets together forming a plurality of passages. At least one of the passages has an entrance and an exit opposite to the entrance. The entrance faces the cover plate, and the exit faces the pedestal. A thickness of one of the sidewall sheets at the entrance is thinner than a thickness of the sidewall sheet at the exit.

公开(公告)号：US12166128B2

公开(公告)日：2024-12-10

申请号：US18360344

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.