公开(公告)号：US20120074537A1

公开(公告)日：2012-03-29

申请号：US12888434

申请日：2010-09-23

Applicant: Sung Mun JUNG ,  Swee Tuck WOO ,  Sanford CHU ,  Liang Choo HSIA

Inventor： Sung Mun JUNG ,  Swee Tuck WOO ,  Sanford CHU ,  Liang Choo HSIA

IPC: H01L29/51 ,  H01L21/31 ,  H01L21/66

CPC classification number: H01L29/511 ,  H01L21/02326 ,  H01L21/28282 ,  H01L22/12 ,  H01L22/20 ,  H01L29/792

Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.

Abstract translation: 公开了一种形成装置的方法。 该方法包括提供衬底并在具有成形厚度TFD的衬底上形成器件层。 在具有成形厚度TFC的基板上形成覆盖层。 形成覆盖层消耗所需量的器件层，以使器件层的厚度达到目标厚度TTD。 将覆盖层的厚度从TFC调整到大约目标厚度TTC。

公开(公告)号：US20120074482A1

公开(公告)日：2012-03-29

申请号：US12888431

申请日：2010-09-23

Applicant: Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

Inventor： Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.

Abstract translation: 公开了一种形成装置的方法。 该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。 在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 形成第一和第二晶体管的第一和第二结。 该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。

公开(公告)号：US20120074483A1

公开(公告)日：2012-03-29

申请号：US12888437

申请日：2010-09-23

Applicant: Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

Inventor： Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7881 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.

Abstract translation: 公开了一种形成装置的方法。 该方法包括提供准备有单元区域的基板，并在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括围绕第一子栅极的第二子栅极。 第一栅极的第一和第二子栅极由第一栅极介电层分开。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 该方法还包括形成第一和第二晶体管的第一和第二结。 第一栅极端子形成并耦合到第一晶体管的第二子栅极。 第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。

公开(公告)号：US20120139046A1

公开(公告)日：2012-06-07

申请号：US13366355

申请日：2012-02-06

Applicant: Chung Foong TAN ,  Eng Huat TOH ,  Jae Gon LEE ,  Sanford CHU

Inventor： Chung Foong TAN ,  Eng Huat TOH ,  Jae Gon LEE ,  Sanford CHU

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618

Abstract: Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

Abstract translation: 本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。 沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。 该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。 掩埋绝缘介质层设置成与源区域的下表面邻接。

公开(公告)号：US20090072310A1

公开(公告)日：2009-03-19

申请号：US11855168

申请日：2007-09-14

Applicant: Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

Inventor： Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

Abstract: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

Abstract translation: 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

公开(公告)号：US20090315152A1

公开(公告)日：2009-12-24

申请号：US12144652

申请日：2008-06-24

Applicant: Shyue Seng TAN ,  Lee Wee TEO ,  Yung Fu CHONG ,  Elgin QUEK ,  Sanford CHU

Inventor： Shyue Seng TAN ,  Lee Wee TEO ,  Yung Fu CHONG ,  Elgin QUEK ,  Sanford CHU

IPC: H01L29/32 ,  H01L21/76

CPC classification number: H01L29/66537 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3223 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/532 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract translation: 提出了一种形成装置的方法。 该方法包括提供具有第一和第二区域的结构。 在第一和第二区域的至少一部分之间形成扩散阻挡层。 扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

公开(公告)号：US20070268093A1

公开(公告)日：2007-11-22

申请号：US11832642

申请日：2007-08-01

Applicant: Suh Fei LIM ,  Kok Wai CHEW ,  Sanford CHU ,  Michael CHENG

Inventor： Suh Fei LIM ,  Kok Wai CHEW ,  Sanford CHU ,  Michael CHENG

IPC: H03H7/00

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H03H2001/0078 ,  H01L2924/00

Abstract: Embodiments of the invention provide an integrated circuit structure comprising: a substrate; a shield structure comprising a shield member and a ground strap formed on the substrate, wherein the shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.

Abstract translation: 本发明的实施例提供一种集成电路结构，包括：基板; 屏蔽结构，其包括形成在所述基板上的屏蔽构件和接地带，其中所述屏蔽构件包括非金属部分，并且所述接地带包括金属部分。

公开(公告)号：US20110079850A1

公开(公告)日：2011-04-07

申请号：US12964753

申请日：2010-12-10

Applicant: Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

Inventor： Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

IPC: H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

Abstract: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

Abstract translation: 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

公开(公告)号：US20110042743A1

公开(公告)日：2011-02-24

申请号：US12916653

申请日：2010-11-01

Applicant: Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

Inventor： Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

Abstract translation: 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

公开(公告)号：US20110049625A1

公开(公告)日：2011-03-03

申请号：US12550407

申请日：2009-08-31

Applicant: Chung Foong TAN ,  Eng Huat TOH ,  Jae Gon LEE ,  Sanford CHU

Inventor： Chung Foong TAN ,  Eng Huat TOH ,  Jae Gon LEE ,  Sanford CHU

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618

Abstract: Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

Abstract translation: 本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。 沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。 该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。 掩埋绝缘介质层设置成与源区域的下表面邻接。