公开(公告)号：US07595237B2

公开(公告)日：2009-09-29

申请号：US11740939

申请日：2007-04-27

Applicant: Xiaoyu Chen ,  Donghua Liu ,  Sung Mun Jung ,  Swee Tuck Woo ,  Rachel Low ,  Louis Lim ,  Siow Lee Chwa

Inventor： Xiaoyu Chen ,  Donghua Liu ,  Sung Mun Jung ,  Swee Tuck Woo ,  Rachel Low ,  Louis Lim ,  Siow Lee Chwa

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0433 ,  H01L21/28282 ,  H01L29/66833

Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.

Abstract translation: 非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。 存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。 存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

公开(公告)号：US20070207558A1

公开(公告)日：2007-09-06

申请号：US11308061

申请日：2006-03-04

Applicant: Sung Mun Jung ,  Ching Dong Wang ,  Louis Yoke Leng Lim ,  Swee Tuck Woo ,  Donghua Liu ,  Xiaoyu Chen

Inventor： Sung Mun Jung ,  Ching Dong Wang ,  Louis Yoke Leng Lim ,  Swee Tuck Woo ,  Donghua Liu ,  Xiaoyu Chen

IPC: H01L21/00

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.

Abstract translation: 一种集成电路存储器系统，包括形成有等间隔开的浅沟槽隔离区域的衬底。 在等离子间隔开的浅沟槽隔离区域之间的衬底内形成有源区和虚拟有源区。 在活跃区域内形成源头和排水渠。 提供在第一方向上延伸的字线和源极线，并且沿第二方向延伸的位线。 在虚拟有源区域上形成接触区域，用于将字线和源极线捆扎到位线。

公开(公告)号：US07074682B2

公开(公告)日：2006-07-11

申请号：US10951503

申请日：2004-09-27

Applicant: Jum Soo Kim ,  Sung Mun Jung

Inventor： Jum Soo Kim ,  Sung Mun Jung

IPC: H01L21/71

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate oxide lines on the semiconductor substrate between the trench lines, forming gate lines on the trench lines and the gate oxide lines, the gate lines being substantially perpendicular to the trench lines, etching the gate oxide lines and trench lines positioned between the gate lines, to form an etched region forming self aligned sources (SASs) by implanting impurity ions into the etched region, forming spacers on sidewalls of the gate lines, and implanting impurity ions in the SAS region using the spacers as a mask.

Abstract translation: 为了提供防止通道长度缩短以及降低SAS电阻的方法，根据本发明的半导体器件通过在半导体衬底上形成连续的线性沟槽线，在半导体衬底上形成栅极氧化物线 沟槽线之间的衬底，在沟槽线上形成栅极线和栅极氧化物线，栅极线基本上垂直于沟槽线，蚀刻位于栅极线之间的栅极氧化物线和沟槽线，以形成蚀刻区域 通过将杂质离子注入到蚀刻区域中形成自对准源（SAS），在栅极线的侧壁上形成间隔物，并且使用间隔物作为掩模将杂质离子注入到SAS区域中。

公开(公告)号：US07056647B2

公开(公告)日：2006-06-06

申请号：US10749648

申请日：2003-12-30

Applicant: Sung Mun Jung ,  Chang Hun Han

Inventor： Sung Mun Jung ,  Chang Hun Han

IPC: G03C5/00

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11531

Abstract: A flash memory device having a reduced source resistance and a fabrication method thereof are disclosed. An example flash memory includes a cell region including a gate, a source line, a drain contact, and a cell trench area for device isolation on a silicon substrate. The example flash memory also includes a peripheral region positioned around the cell region and including a subsidiary circuit and a peripheral trench area for device isolation on the silicon substrate, wherein the cell trench area of the cell region is shallower than the peripheral trench area of the peripheral region.

Abstract translation: 公开了一种具有降低的源极电阻的闪存器件及其制造方法。 示例性闪存包括包括栅极，源极线，漏极接触和用于硅衬底上的器件隔离的沟道区域的单元区域。 示例性闪存还包括围绕单元区域定位的外围区域，并且包括用于在硅衬底上进行器件隔离的辅助电路和外围沟槽区域，其中，单元区域的单元沟槽区域比所述栅极区域的外围沟槽区域浅 周边地区。

公开(公告)号：US06759299B2

公开(公告)日：2004-07-06

申请号：US10321720

申请日：2002-12-18

Applicant: Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

Inventor： Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

IPC: H01L218247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: The present invention relates to a method of manufacturing a flash memory device. In the method, a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device. As the process for forming the LDD structure for the low voltage is omitted, the cost is reduced in the entire process of manufacturing the flash memory device. Also, as the junction breakdown voltage of the low-voltage transistor is increased and current is increased, the device characteristics is improved

Abstract translation: 本发明涉及一种制造闪速存储器件的方法。 在该方法中，当在闪速存储器件的制造过程中形成周边区域时，形成低压晶体管，以使DDD结构与高电压晶体管相同。 由于省略了用于形成用于低电压的LDD结构的工艺，所以在制造闪存器件的整个过程中降低了成本。 此外，随着低压晶体管的结击穿电压增加并且电流增加，器件特性得到改善

公开(公告)号：US08541273B2

公开(公告)日：2013-09-24

申请号：US12888434

申请日：2010-09-23

Applicant: Sung Mun Jung ,  Swee Tuck Woo ,  Sanford Chu ,  Liang Choo Hsia

Inventor： Sung Mun Jung ,  Swee Tuck Woo ,  Sanford Chu ,  Liang Choo Hsia

IPC: H01L21/8238

CPC classification number: H01L29/511 ,  H01L21/02326 ,  H01L21/28282 ,  H01L22/12 ,  H01L22/20 ,  H01L29/792

Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.

Abstract translation: 公开了一种形成装置的方法。 该方法包括提供衬底并在具有成形厚度TFD的衬底上形成器件层。 在具有成形厚度TFC的基板上形成覆盖层。 形成覆盖层消耗所需量的器件层，以使器件层的厚度达到目标厚度TTD。 将覆盖层的厚度从TFC调整到大约目标厚度TTC。

公开(公告)号：US20120074482A1

公开(公告)日：2012-03-29

申请号：US12888431

申请日：2010-09-23

Applicant: Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

Inventor： Sung Mun JUNG ,  Kian Hong LIM ,  Jianbo YANG ,  Swee Tuck WOO ,  Sanford CHU

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.

Abstract translation: 公开了一种形成装置的方法。 该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。 在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 形成第一和第二晶体管的第一和第二结。 该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。

公开(公告)号：US07553724B2

公开(公告)日：2009-06-30

申请号：US10029394

申请日：2001-12-28

Applicant: Jum Soo Kim ,  Sung Mun Jung ,  Min Kuck Cho ,  Young Bok Lee

Inventor： Jum Soo Kim ,  Sung Mun Jung ,  Min Kuck Cho ,  Young Bok Lee

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/792

Abstract: The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.

Abstract translation: 本发明涉及制造代码地址存储器（CAM）单元的方法。 本发明使用其中在闪存单元中的浮栅和控制栅之间的氧化物膜和氮化物膜作为栅极绝缘膜堆叠在CAM单元中的半导体衬底和栅极之间的电介质膜。 因此，本发明可以减小外围电路区域的面积并稳定地确保修复数据，因为可以在低工作电压下稳定地驱动CAM单元，因此不需要附加的升压电路。

公开(公告)号：US20080266944A1

公开(公告)日：2008-10-30

申请号：US11740939

申请日：2007-04-27

Applicant: Xiaoyu Chen ,  Donghua Liu ,  Sung Mun Jung ,  Swee Tuck Woo ,  Rachel Low ,  Louis Lim ,  Siow Lee Chwa

Inventor： Xiaoyu Chen ,  Donghua Liu ,  Sung Mun Jung ,  Swee Tuck Woo ,  Rachel Low ,  Louis Lim ,  Siow Lee Chwa

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0433 ,  H01L21/28282 ,  H01L29/66833

Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.

Abstract translation: 非易失性存储单元包括串联耦合的存取晶体管和存储晶体管。 存储器单元形成在薄栅极上，该薄栅极具有薄栅极电介质的晶体管。 存取晶体管是混合晶体管，其包括形成在薄栅极阱上的具有厚栅介电层的栅极。

公开(公告)号：US20080014707A1

公开(公告)日：2008-01-17

申请号：US11485949

申请日：2006-07-12

Applicant: Sung Mun Jung ,  Yoke Leng Louis Lim ,  Sripad Nagarad ,  Dong Kyun Sohn ,  Dong Hua Liu ,  Xiao Yu Chen ,  Rachel Low

Inventor： Sung Mun Jung ,  Yoke Leng Louis Lim ,  Sripad Nagarad ,  Dong Kyun Sohn ,  Dong Hua Liu ,  Xiao Yu Chen ,  Rachel Low

IPC: H01L21/76

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.

Abstract translation: 在非限制性实例中，我们提供具有细胞区域和非细胞区域的底物。 我们在衬底上形成隧道介电层，电荷存储层，顶部绝缘层（例如ONO）。 然后我们在顶部绝缘层上形成导电焊盘层。 我们在焊盘层，电荷存储层和隧道电介质层中形成隔离沟槽并进入衬底。 我们在隔离沟中形成隔离区。 我们去除非单元区域中的焊盘层，电荷存储层和隧道介电层。 我们在衬垫层和衬底表面上形成栅极层。 我们完成以形成单元区域中的存储器（例如SONOS）器件和衬底的非单元区域中的其他器件。