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公开(公告)号：US11038521B1
公开(公告)日：2021-06-15
申请号：US16805336
申请日：2020-02-28
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Srisai R. Seethamraju , Russell Croman , James D. Barnette
Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.
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公开(公告)号：US10951216B1
公开(公告)日：2021-03-16
申请号：US16600793
申请日：2019-10-14
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.
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公开(公告)号：US10651862B1
公开(公告)日：2020-05-12
申请号：US16441898
申请日：2019-06-14
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , Krishnan Balakrishnan
Abstract: A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.
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公开(公告)号：US11342926B2
公开(公告)日：2022-05-24
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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公开(公告)号：US11245406B2
公开(公告)日：2022-02-08
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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Patent Agency Ranking
公开(公告)号：US20210184687A1
公开(公告)日：2021-06-17
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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公开(公告)号：US10727844B1
公开(公告)日：2020-07-28
申请号：US16427826
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette , Krishnan Balakrishnan
Abstract: A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
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公开(公告)号：US10693475B1
公开(公告)日：2020-06-23
申请号：US16427837
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette
IPC: H03L7/093
Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.
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公开(公告)号：US20210409031A1
公开(公告)日：2021-12-30
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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公开(公告)号：US20200379412A1
公开(公告)日：2020-12-03
申请号：US16428288
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Krishnan Balakrishnan , James D. Barnette
Abstract: A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.
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