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公开(公告)号：US20210409031A1
公开(公告)日：2021-12-30
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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公开(公告)号：US20210391864A1
公开(公告)日：2021-12-16
申请号：US16901814
申请日：2020-06-15
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Timothy A. Monk , William Anker , Srisai Rao Seethamraju
Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.
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公开(公告)号：US11316522B2
公开(公告)日：2022-04-26
申请号：US16901814
申请日：2020-06-15
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Timothy A. Monk , William Anker , Srisai Rao Seethamraju
Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.
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公开(公告)号：US11245406B2
公开(公告)日：2022-02-08
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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