公开(公告)号：US20210184687A1

公开(公告)日：2021-06-17

申请号：US17186180

申请日：2021-02-26

Applicant: Silicon Laboratories Inc.

Inventor： James D. Barnette ,  William Anker ,  Xue-Mei Gong

IPC: H03L7/099 ,  H03L7/087

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

公开(公告)号：US10951216B1

公开(公告)日：2021-03-16

申请号：US16600793

申请日：2019-10-14

Applicant: Silicon Laboratories Inc.

Inventor： James D. Barnette ,  William Anker ,  Xue-Mei Gong

IPC: H03L7/087 ,  H03L7/099

Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.

公开(公告)号：US20210391864A1

公开(公告)日：2021-12-16

申请号：US16901814

申请日：2020-06-15

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Timothy A. Monk ,  William Anker ,  Srisai Rao Seethamraju

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/14 ,  H03L7/197

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

公开(公告)号：US11342926B2

公开(公告)日：2022-05-24

申请号：US17186180

申请日：2021-02-26

Applicant: Silicon Laboratories Inc.

Inventor： James D. Barnette ,  William Anker ,  Xue-Mei Gong

IPC: H03L7/099 ,  H03L7/087

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

公开(公告)号：US11316522B2

公开(公告)日：2022-04-26

申请号：US16901814

申请日：2020-06-15

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Timothy A. Monk ,  William Anker ,  Srisai Rao Seethamraju

IPC: H03L7/099 ,  H03L7/08 ,  H03L7/197 ,  H03L7/14

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.