公开(公告)号：US20210409031A1

公开(公告)日：2021-12-30

申请号：US16917828

申请日：2020-06-30

Applicant: Silicon Laboratories Inc.

Inventor： Harihara Subramanian Ranganathan ,  Xue-Mei Gong ,  James D. Barnette ,  Nathan J. Shashoua ,  Srisai Rao Seethamraju

IPC: H03L7/197 ,  H03L7/093

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

公开(公告)号：US11245406B2

公开(公告)日：2022-02-08

申请号：US16917828

申请日：2020-06-30

Applicant: Silicon Laboratories Inc.

Inventor： Harihara Subramanian Ranganathan ,  Xue-Mei Gong ,  James D. Barnette ,  Nathan J. Shashoua ,  Srisai Rao Seethamraju

IPC: H03L7/197 ,  H03L7/093

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.