公开(公告)号：US20200379412A1

公开(公告)日：2020-12-03

申请号：US16428288

申请日：2019-05-31

Applicant: Silicon Laboratories Inc.

Inventor： Krishnan Balakrishnan ,  James D. Barnette

IPC: G04F10/00 ,  H03K5/00 ,  H03L7/081 ,  G06F1/08

Abstract: A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

公开(公告)号：US10727845B1

公开(公告)日：2020-07-28

申请号：US16451752

申请日：2019-06-25

Applicant: Silicon Laboratories Inc.

Inventor： Krishnan Balakrishnan ,  James D. Barnette

IPC: H03L7/099 ,  H03L7/093

Abstract: A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.

公开(公告)号：US10651862B1

公开(公告)日：2020-05-12

申请号：US16441898

申请日：2019-06-14

Applicant: Silicon Laboratories Inc.

Inventor： James D. Barnette ,  Krishnan Balakrishnan

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/18 ,  H03K3/03 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033

Abstract: A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.

公开(公告)号：US10727844B1

公开(公告)日：2020-07-28

申请号：US16427826

申请日：2019-05-31

Applicant: Silicon Laboratories Inc.

Inventor： Xue-Mei Gong ,  James D. Barnette ,  Krishnan Balakrishnan

IPC: H03L1/02 ,  H03L7/093 ,  H03K5/26

Abstract: A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.