-
公开(公告)号：US20190305783A1
公开(公告)日：2019-10-03
申请号：US15944567
申请日：2018-04-03
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Russell Croman , Brian G. Drost
Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.
-
公开(公告)号：US20170288764A1
公开(公告)日：2017-10-05
申请号：US15086248
申请日：2016-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Russell Croman , Nebojsa Stanic , Michael Johnson , Dan B. Kasha , Michael R. May
CPC classification number: H04B7/08 , H04B1/0064 , H04B1/0075 , H04B1/16
Abstract: In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.
-
公开(公告)号：US11205696B2
公开(公告)日：2021-12-21
申请号：US16726477
申请日：2019-12-24
Applicant: Silicon Laboratories Inc.
Inventor： Dan B. Kasha , Russell Croman , Stefan N. Mastovich , Thomas C. Fowler
Abstract: An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.
-
公开(公告)号：US11038521B1
公开(公告)日：2021-06-15
申请号：US16805336
申请日：2020-02-28
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Srisai R. Seethamraju , Russell Croman , James D. Barnette
Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.
-
公开(公告)号：US10128930B2
公开(公告)日：2018-11-13
申请号：US15710967
申请日：2017-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Russell Croman , Nebojsa Stanic , Michael Johnson , Dan B. Kasha , Michael R. May
Abstract: In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.
-
Patent Agency Ranking
公开(公告)号：US09379676B2
公开(公告)日：2016-06-28
申请号：US14166370
申请日：2014-01-28
Applicant: Silicon Laboratories Inc.
Inventor： Michael S. Johnson , Russell Croman
CPC classification number: H03F1/56 , H03F3/45941 , H03F3/45977 , H03F3/45995 , H03F2203/45048 , H03F2203/45078 , H03F2203/45082 , H03F2203/45171 , H03F2203/45522 , H03F2203/45538 , H03F2203/45576 , H03F2203/45591 , H03F2203/45616
Abstract: Circuitry and methods are disclosed that may employ common mode calibration circuitry configured to at least partially calibrate out impedance differences or mismatches between the differential signal paths of differential signal circuitry. The common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry that includes a differential amplifier to reject common mode noise, and may be used to reduce or substantially eliminate any external and/or internal difference in signal path resistance that exists between the differential signal paths of the integrated differential signal circuitry. A common mode calibration signal may be internally or externally applied to the signal inputs of differential signal circuitry, and used to determine a setting for the common mode calibration circuitry that at least partially calibrates out impedance differences or mismatches between the differential signal paths of differential signal circuitry.
Abstract translation: 公开了可以采用共模校准电路的电路和方法，其配置为至少部分地校准差分信号电路的差分信号路径之间的阻抗差或失配。 共模校准电路可以集成为集成差分信号电路的内部部分，其包括用于抑制共模噪声的差分放大器，并且可以用于减少或基本消除存在的信号路径电阻中的任何外部和/或内部差异 在集成差分信号电路的差分信号路径之间。 共模校准信号可以在内部或外部施加到差分信号电路的信号输入端，并且用于确定共模校准电路的设置，其至少部分地校准差分信号的差分信号路径之间的阻抗差或失配 电路。
-
公开(公告)号：US20210193791A1
公开(公告)日：2021-06-24
申请号：US16726477
申请日：2019-12-24
Applicant: Silicon Laboratories Inc.
Inventor： Dan B. Kasha , Russell Croman , Stefan N. Mastovich , Thomas C. Fowler
Abstract: An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.
-
公开(公告)号：US20180026701A1
公开(公告)日：2018-01-25
申请号：US15710967
申请日：2017-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Russell Croman , Nebojsa Stanic , Michael Johnson , Dan B. Kasha , Michael R. May
CPC classification number: H04B7/08 , H04B1/0064 , H04B1/0075 , H04B1/16
Abstract: In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.
-
公开(公告)号：US20150214911A1
公开(公告)日：2015-07-30
申请号：US14166370
申请日：2014-01-28
Applicant: Silicon Laboratories Inc.
Inventor： Michael S. Johnson , Russell Croman
CPC classification number: H03F1/56 , H03F3/45941 , H03F3/45977 , H03F3/45995 , H03F2203/45048 , H03F2203/45078 , H03F2203/45082 , H03F2203/45171 , H03F2203/45522 , H03F2203/45538 , H03F2203/45576 , H03F2203/45591 , H03F2203/45616
Abstract: Circuitry and methods are disclosed that may employ common mode calibration circuitry configured to at least partially calibrate out impedance differences or mismatches between the differential signal paths of differential signal circuitry. The common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry that includes a differential amplifier to reject common mode noise, and may be used to reduce or substantially eliminate any external and/or internal difference in signal path resistance that exists between the differential signal paths of the integrated differential signal circuitry. A common mode calibration signal may be internally or externally applied to the signal inputs of differential signal circuitry, and used to determine a setting for the common mode calibration circuitry that at least partially calibrates out impedance differences or mismatches between the differential signal paths of differential signal circuitry.
Abstract translation: 公开了可以采用共模校准电路的电路和方法，其配置为至少部分地校准差分信号电路的差分信号路径之间的阻抗差或失配。 共模校准电路可以集成为集成差分信号电路的内部部分，其包括用于抑制共模噪声的差分放大器，并且可以用于减少或基本消除存在的信号路径电阻中的任何外部和/或内部差异 在集成差分信号电路的差分信号路径之间。 共模校准信号可以在内部或外部施加到差分信号电路的信号输入端，并且用于确定共模校准电路的设置，其至少部分地校准差分信号的差分信号路径之间的阻抗差或失配 电路。
-
公开(公告)号：US10419047B1
公开(公告)日：2019-09-17
申请号：US16225722
申请日：2018-12-19
Applicant: Silicon Laboratories Inc.
Inventor： Carl Harry Alelyunas , Russell Croman , Thomas Glen Ragan , Tarang Shah
Abstract: In one embodiment, a noise cancellation circuit includes: a window generator to generate a window having a first set of samples; a band splitter to split the window into pairs of symmetric frequency components; a processing circuit, for each of the pairs, to: compare a first magnitude of a first symmetric frequency component to a second magnitude of a second symmetric frequency component and modify one of the components based at least in part on the comparison; an integrator to integrate the pairs output from the processing circuit; and a second window generator to generate a second window having a second set of samples.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.019 seconds)
