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公开(公告)号：US10367081B2
公开(公告)日：2019-07-30
申请号：US15520375
申请日：2017-04-06
发明人： Longqiang Shi
IPC分类号： H01L29/12 , H01L29/66 , H01L21/02 , H01L29/786 , H01L21/477 , H01L21/385
摘要： The present disclosure provides a thin film transistor (TFT) and its manufacturing method. The method includes the following steps: sequentially depositing a buffer layer and a shielding layer on a substrate; forming an IGZO layer on and covering the shielding layer; processing the IGZO layer by annealing so that a portion of the IGZO layer is diffused by the buffer layer and has a conductor property; and forming a source and a drain so that the source and drain contact the portion of the IGZO layer. The present disclosure, through annealing the IGZO layer, the buffer layer makes portions of the IGZO layer contacting the source and the drain to have conductor property, thereby avoiding the prior art's complex process, simplifying the manufacturing of the IGZO TFT, and enhancing the production efficiency.
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公开(公告)号：US10367066B2
公开(公告)日：2019-07-30
申请号：US15328945
申请日：2017-01-11
发明人： Longqiang Shi
IPC分类号： H01L29/24 , H01L21/322 , H01L21/443 , H01L29/45 , H01L29/66 , H01L29/786
摘要： Disclosed are a thin film transistor and a method for manufacturing the same, which relates to the technical field of display. Each of a source and a drain of the thin film transistor includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer is in contact with an IGZO (indium gallium zinc oxide) layer, and a metal diffusion layer is provided at a contact face. Meanwhile, disclosed is a method for manufacturing the thin film transistor: sequentially obtaining the first metal layer, the second metal layer, and the third metal layer through deposition; then obtaining PV layers; and then performing high temperature annealing treatment on the PV layers to diffuse a metal within the first metal layer into the IGZO layer, thereby forming a metal diffusion layer. The metal diffusion layer forms Ohmic contact between the first metal layer and the IGZO layer, thus reducing contact resistance both between the source and the IGZO layer and between the drain and the IGZO layer.
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3.发明授权公开(公告)号：US10276120B2
公开(公告)日：2019-04-30
申请号：US15327640
申请日：2017-01-16
发明人： Longqiang Shi , Shu-Jhih Chen
摘要： The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.
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公开(公告)号：US10262614B2
公开(公告)日：2019-04-16
申请号：US15326952
申请日：2017-01-16
发明人： Longqiang Shi , Congwei Liao
IPC分类号： G09G3/36
摘要： The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally.
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公开(公告)号：US10204562B2
公开(公告)日：2019-02-12
申请号：US15325149
申请日：2017-01-09
发明人： Longqiang Shi
IPC分类号： G09G3/20 , G09G3/36 , G09G3/3266
摘要： The pull-down control signal point relates to a scanning driving circuit and a display panel. The scanning driving circuit includes a pull-up control circuit configured for pulling up a level of a pull-up control signal point to be a high level or for pulling down the level of the pull-up control signal point to be a low level, a pull-down control circuit configured for pulling down the level of a pull-down control signal point to be the high level or for pulling down the level of the pull-down control signal point to be the low level, and the pull-down control circuit connects to the pull-up control circuit, and a scanning output circuit connects to the pull-up control circuit and the pull-down control circuit, and the scanning output circuit is configured for outputting the scanning driving signals of the high level or of the low level.
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公开(公告)号：US10181297B2
公开(公告)日：2019-01-15
申请号：US15544016
申请日：2017-04-28
发明人： Longqiang Shi
摘要： Disclosed is a driving circuit, comprising first to fifth electrical switches, a driving electrical switch and a capacitor. The control end and second end of the first switch are coupled to a driving scan line and a driving switch second end. The control end, first end and second end of the driving switch are coupled to the capacitor, a second switch second end and a fourth switch first end. The control end of the second switch is coupled to the driving scan line. The control end of the third switch is coupled to a first compensation scan line. The control end and second end of the fourth switch are coupled to a fifth switch second end and an organic light emitting diode anode. The control end and first end of the fifth switch are coupled to a second compensation scan line and the third switch control end.
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公开(公告)号：US20180337333A1
公开(公告)日：2018-11-22
申请号：US15329329
申请日：2017-01-13
发明人： Longqiang Shi
CPC分类号： H01L27/12
摘要： Disclosed are an array substrate of an OLED display device and a method for manufacturing the same. Thin-film transistors having different functions can have different electrical properties. The array substrate includes a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top. A plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor.
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公开(公告)号：US09978778B2
公开(公告)日：2018-05-22
申请号：US14759190
申请日：2015-05-27
发明人： Longqiang Shi , Baixiang Han
IPC分类号： H01L21/02 , H01L27/12 , H01L29/24 , H01L29/786 , H01L29/49 , H01L21/443 , G09G3/3225
CPC分类号： H01L27/124 , G09G3/3225 , G09G2300/043 , G09G2300/0465 , H01L21/02565 , H01L21/02631 , H01L21/443 , H01L27/1225 , H01L27/127 , H01L29/24 , H01L29/4908 , H01L29/78648 , H01L29/7869
摘要： The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate arranges a connection electrode (83) that connects two dual gate TFTs in a third metal layer to prevent the design rules of a connection electrode and a second metal layer of the prior art techniques from being narrowed due to the connection electrode being collectively present on the second metal layer with signal lines of a data line and a voltage supply line so as to facilitate increase of an aperture ratio and definition of a display panel. The present invention provides a TFT substrate structure, which has a simple structure and possesses a high aperture ratio and high definition.
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公开(公告)号：US09960283B2
公开(公告)日：2018-05-01
申请号：US14416767
申请日：2014-12-22
发明人： Longqiang Shi , Zhiyuan Zeng , Hejing Zhang , Yutong Hu
IPC分类号： H01L29/02 , H01L29/786 , H01L29/417
CPC分类号： H01L29/78696 , H01L29/41733 , H01L29/4175 , H01L29/78648
摘要： Disclosed is a thin-film transistor. The thin-film transistor includes: a substrate; a first gate, a first gate insulation layer, a semiconductor layer, an etching stop layer, and the second gate stacked on a surface of the substrate, in which the semiconductor layer has a thickness of 200 nm-2000 nm; the etching stop layer includes a first via and a second via formed therein; and the first via and the second via are arranged to each correspond to the semiconductor layer; and a source and a drain respectively extending through the first via and the second via to connect to the semiconductor layer. The thin-film transistor has an increased ON-state current and switching speed.
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10.发明授权公开(公告)号：US09947699B2
公开(公告)日：2018-04-17
申请号：US15650972
申请日：2017-07-16
发明人： Shimin Ge , Hejing Zhang , Chihyuan Tseng , Chihyu Su , Wenhui Li , Longqiang Shi , Xiaowen Lv
CPC分类号： H01L27/1288 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/24 , H01L29/4908 , H01L29/78648 , H01L29/7869
摘要： A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.
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