公开(公告)号：US4952796A

公开(公告)日：1990-08-28

申请号：US235365

申请日：1988-08-23

Applicant: Serge Fruhauf ,  Laurent Sourgen

Inventor： Serge Fruhauf ,  Laurent Sourgen

IPC: G01J1/02 ,  G06F12/14 ,  G06F21/06 ,  G06K19/07 ,  G06K19/073 ,  G06K19/10 ,  G07F7/10 ,  H01L27/144 ,  H01L31/02 ,  H01L31/10 ,  H03F3/08

CPC classification number: G07F7/1008 ,  G06K19/073 ,  G06K19/07372 ,  G06Q20/341 ,  G07F7/082 ,  H01L23/576 ,  H01L27/1443 ,  H01L31/02019 ,  H01L2924/0002

Abstract: In a semi-conducting integrated circuit, there is made a light detection circuit, the output signal of which can be used to counter manipulations by dishonest persons who undertake a decapsulation or a removal from the card when the integrated circuit is inserted in a bank type card, or even a depassivation of the upper protective layer of this integrated circuit, in order to reveal the secret functioning of the circuit or to modify its characteristics. The detector comprises a current generator delivering a current of limited intensity which flows into a reversed biased electronic junction. When the junction is subjected to light, the reverse current that can be allowed into the junction increases. Since the current generator is not capable of putting through stronger current, the voltage at the terminals of the junction drops. This drop in voltage is used as information that reveals the illumination.

Abstract translation: 在半导体集成电路中，形成光检测电路，其输出信号可用于对集成电路插入银行类型中进行解封装或从卡中取出的不诚实的人进行操纵 卡，甚至是该集成电路的上保护层的去激活，以揭示电路的秘密功能或修改其特性。 该检测器包括传递有限强度的电流的电流发生器，其流入反向偏置的电子结。 当结点经受光时，可以允许进入结的反向电流增加。 由于电流发生器不能施加更强的电流，所以结点的电压下降。 这种电压下降被用作显示照明的信息。

公开(公告)号：US4932053A

公开(公告)日：1990-06-05

申请号：US431534

申请日：1989-11-03

Applicant: Serge Fruhauf ,  Laurent Sourgen

Inventor： Serge Fruhauf ,  Laurent Sourgen

IPC: G06F12/14 ,  G06F21/06 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C16/22

CPC classification number: G07F7/1008 ,  G06K19/073 ,  G06Q20/341 ,  G07F7/082 ,  G11C16/22 ,  G11C7/24 ,  G06F2207/7219

Abstract: The disclosure concerns the safety of the confidential information contained in integrated circuits. In a certain number of integrated circuit applications and, more particularly, in the circuits contained in cards known as "chip cards", it is necessary to prohibit access by unauthorized persons to confidential information stored in a memory of the circuit. To prevent the fraudulent practice of examining the current consumption at the terminals of the integrated circuit during an operation of reading or writing in the memory, a protection circuit is used. This protection circuit actuates the simulation, according to a pseudo-random sequence generated by a generator, of current consumption values identical to those of real memory cells.

Abstract translation: 本公开涉及集成电路中包含的机密信息的安全性。 在一定数量的集成电路应用中，更具体地说，在被称为“芯片卡”的卡中包含的电路中，有必要禁止未经授权的人访问存储在电路的存储器中的机密信息。 为了防止在读取或写入存储器的操作期间检查集成电路的端子处的电流消耗的欺诈做法，使用保护电路。 该保护电路根据由发生器产生的伪随机序列致动与真实存储器单元相同的电流消耗值的模拟。

公开(公告)号：US5619165A

公开(公告)日：1997-04-08

申请号：US417852

申请日：1995-04-06

Applicant: Richard P. Fournel ,  Laurent Sourgen

Inventor： Richard P. Fournel ,  Laurent Sourgen

IPC: G01R19/165 ,  G06F1/28 ,  H03K17/22 ,  G05F1/00

CPC classification number: G01R19/16519

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Abstract translation: 用于低功率集成电路的电源电压监控电路，其中通过开关电容器链的电荷共享用于将电源电压耦合到动态感测节点。 动态感应节点驱动一个半锁定，在无报警状态下稳定。

公开(公告)号：US5099451A

公开(公告)日：1992-03-24

申请号：US272123

申请日：1988-11-16

Applicant: Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

Inventor： Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/005 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/06 ,  G11C16/10

Abstract: To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.

Abstract translation: 为了避免差异化，在制造中，在相同存储器阵列的随机存取存储器单元和只读存储器单元之间，存储单元都由相同的技术制成。 这些存储单元基本上采用浮置晶体管。 随机存取存储器单元以静态方式通过在晶体管的浮置栅极中注入或不注入电子来编程。 只读存储器单元通过选择性地注入杂质而不是在这些存储单元的浮置栅晶体管的导通通道中被置于编程状态或未编程状态。 改进了对这些存储器单元的隐藏内容的改进的隐藏，同时提高了制作原型的条件。

公开(公告)号：US5978915A

公开(公告)日：1999-11-02

申请号：US573942

申请日：1995-12-18

Applicant: Mathieu Lisart ,  Laurent Sourgen

Inventor： Mathieu Lisart ,  Laurent Sourgen

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00 ,  G06F11/00 ,  G11C17/00

CPC classification number: G06F12/1425

Abstract: The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

Abstract translation: 通过创建接收要保护的指令字和/或数据字的地址的决定表来保护对集成电路的存储字的访问，并且还接收分配给一个字的控制字的控制位的地址 被保护。 可以看出，这种操作模式通过使用以有线电路形式制定的决策表以及通过分配给要控制的每个存储器字的控制字的可编程质量而具有更大的灵活性来提供更大的安全性。

公开(公告)号：US5440263A

公开(公告)日：1995-08-08

申请号：US53892

申请日：1993-04-27

Applicant: Richard P. Fournel ,  Laurent Sourgen

Inventor： Richard P. Fournel ,  Laurent Sourgen

IPC: G01R19/165 ,  G06F1/28 ,  H03K17/22 ,  G05F1/00

CPC classification number: G01R19/16519

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

Abstract translation: 用于低功率集成电路的电源电压监控电路，其中通过开关电容器链的电荷共享用于将电源电压耦合到动态感测节点。 动态感应节点驱动一个半锁定，在无报警状态下稳定。 在该电路中，如果在该阶段开始时电容器的端子处的电压（该电压等于输入电压的一部分）超过确定的阈值，则在第一阶段中输出的状态切换。 该阈值被确定为用于构建电路的技术参数的函数。 这些技术参数主要是晶体管的阈值电压和形成锁定电路的晶体管的特性。

公开(公告)号：US5264742A

公开(公告)日：1993-11-23

申请号：US857959

申请日：1992-03-26

Applicant: Laurent Sourgen

Inventor： Laurent Sourgen

IPC: G01R31/317 ,  G06F12/14 ,  G07F7/10 ,  G11C29/24 ,  G11C29/52 ,  H03K19/003

CPC classification number: G07F7/1008 ,  G01R31/31701 ,  G01R31/31719 ,  G06F12/1425 ,  G06Q20/341 ,  G06Q20/357 ,  G07F7/082 ,  G11C29/24 ,  G11C29/52 ,  G01R31/31702

Abstract: In order to modify the configuration of an integrated circuit, for example to restrict access by the user to certain functions or certain pieces of data of the circuit, the integrated circuit is provided with a first electronic lock capable of being locked or unlocked during a stage for the testing of the integrated circuit and capable of being irreversibly locked after the end of the testing stage, and a second electronic lock capable of being unlocked only so long as the first lock is unlocked. In this way, the entire circuit can be tested in the form in which it is presented to the user, the locking of the locks being, so to speak, simulated during the test.

Abstract translation: 为了修改集成电路的配置，例如为了限制用户对电路的某些功能或某些数据的访问，集成电路设置有能够在一个阶段被锁定或解锁的第一电子锁 用于集成电路的测试，并且能够在测试阶段结束之后不可逆地锁定，并且只要第一锁定解锁，只能解锁锁定的第二电子锁。 以这种方式，整个电路可以以呈现给用户的形式进行测试，在测试期间锁的锁可以说是模拟的。

公开(公告)号：US5889720A

公开(公告)日：1999-03-30

申请号：US852104

申请日：1997-05-06

Applicant: Mathieu Lisart ,  Laurent Sourgen

Inventor： Mathieu Lisart ,  Laurent Sourgen

IPC: G11C16/12 ,  H03K4/00 ,  G11C13/00

CPC classification number: H03K4/00 ,  G11C16/12

Abstract: To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

Abstract translation: 为了形成用于编程存储器单元的斜坡信号，而不会在控制电路中损失过多的电压，使用P型晶体管将电压上拉电路的输出连接到编程输入。 这表明该P型晶体管然后以恒定电流对存储器阵列充电，促使电压线性增加。 这导致防止被编程的存储单元经受过度突然的电压变化。 显示出通过这样的方式，即使在非常低的电压下也可以使集成电路工作。

公开(公告)号：US5850452A

公开(公告)日：1998-12-15

申请号：US509363

申请日：1995-07-31

Applicant: Laurent Sourgen ,  Sylvie Wuidart

Inventor： Laurent Sourgen ,  Sylvie Wuidart

IPC: G06F21/22 ,  G06F1/00 ,  G06F7/76 ,  G06F21/00 ,  G09C1/00 ,  H01L27/10 ,  H04L9/00

CPC classification number: G06F7/76 ,  G06F21/62 ,  G06F21/72 ,  G06F21/75

Abstract: The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

Abstract translation: 本发明涉及一种用于通过在包括控制单元和至少一个数据总线（DBUS）的可编程电路中的数据位置换进行数字加扰的方法，以在控制单元和多个存储器电路之间传送数据。 它包括根据是否是指令数据，以加扰形式或未加扰形式在总线上进行数据。 并且一些存储器中的数据被加扰。 本发明还涉及一种用于实现置换电路的方法。

公开(公告)号：US5285415A

公开(公告)日：1994-02-08

申请号：US902209

申请日：1992-06-22

Applicant: Eric Depret ,  Laurent Sourgen

Inventor： Eric Depret ,  Laurent Sourgen

IPC: G11C17/00 ,  G06F12/16 ,  G06K19/07 ,  G07F7/08 ,  G07F7/10 ,  G11C16/02 ,  G11C16/10 ,  H03K21/00 ,  G06K5/00 ,  G06F15/30

CPC classification number: G07F7/1008 ,  G06K19/07 ,  G06Q20/341 ,  G07F7/082 ,  G07F7/0866 ,  G11C16/102 ,  G11C16/105

Abstract: An integrated circuit for a passive unit counting memory card comprises p levels (10, 11, 12) of data counting memory. The levels contain corresponding numbers of cases n.sub.1 . . . n.sub.p, a write operation being achieved in a case of an upper rank level each time all the cases of the lower rank level have been enabled, the cases of the lower levels then being erased. The circuit comprises p-1 ghost levels (21, 22) identical to the p-1 upper rank levels of the p counting levels. The addressing logic of the ghost levels is such that the cases of ghost levels are addressed in write phase simultaneously with the cases of the corresponding counting levels and, after a write phase, are addressed in erase phase simultaneously with the cases of the levels of lower rank than the one that has just been enabled.

Abstract translation: 用于无源单元计数存储卡的集成电路包括数据计数存储器的p级（10,11,12）。 级别包含相应数量的病例n1。 。 。 np，每当所有低级别的所有情况都被使能时，在高级别级别的情况下实现写入操作，则较低级别的情况然后被擦除。 该电路包括与p个计数电平的p-1个上限电平相同的p-1个重影电平（21,22）。 幽灵级别的寻址逻辑是这样的：在写入阶段，与相应的计数级别的情况同时处理鬼电平的情况，并且在写入阶段之后，在擦除阶段同时处理较低级别的情况 比刚刚启用的更高。