公开(公告)号：US20080280397A1

公开(公告)日：2008-11-13

申请号：US11760048

申请日：2007-06-08

申请人： Seong Cheol KIM ,  Myung Geun PARK

发明人： Seong Cheol KIM ,  Myung Geun PARK

IPC分类号： H01L21/60 ,  H01L21/44

CPC分类号： H05K3/0052 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/28 ,  H05K2201/0909 ,  H05K2201/0989 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.

摘要翻译： 通过以下步骤制造带状平面基板：将阻焊剂涂覆在包含由划线划分的多个单位基板的基板上; 以及对所施加的阻焊剂进行图案化，以暴露每个单位基板中的电极端子和球状区域，其中执行阻焊剂的图案化以与施加在划线上的阻焊剂部件一起去除以减少早期翘曲 的带状基底。

公开(公告)号：US20080277783A1

公开(公告)日：2008-11-13

申请号：US11760010

申请日：2007-06-08

申请人： Seong Cheol KIM ,  Myung Geun PARK

发明人： Seong Cheol KIM ,  Myung Geun PARK

IPC分类号： H01L23/48

CPC分类号： H05K1/111 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2224/0401

摘要： A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.

摘要翻译： 印刷电路板和使用其的倒装芯片封装被设计成使得存在于具有金属线和阻焊剂的区域中存在的不同热系数与印刷电路板上的其它区域的热应力最小化。 印刷电路板包括绝缘层; 形成在所述绝缘层的一个表面上的第一金属线，并且在其一个端部处具有凸起区域和从所述凸起区域整体延伸的突起; 形成在所述绝缘层的另一个表面上并且在其一个端部处具有球形区域的第二金属线; 通过绝缘层形成的通孔金属线，以将第一和第二金属线彼此连接; 以及形成在绝缘层的上表面和下表面上的阻焊剂，以暴露凸起部分和球状区域。

公开(公告)号：US20120205802A1

公开(公告)日：2012-08-16

申请号：US13453116

申请日：2012-04-23

申请人： Seong Cheol KIM ,  Myung Geun PARK

发明人： Seong Cheol KIM ,  Myung Geun PARK

IPC分类号： H01L23/498

CPC分类号： H05K1/111 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2224/0401

摘要： A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.

摘要翻译： 印刷电路板和使用其的倒装芯片封装被设计成使得存在于具有金属线和阻焊剂的区域中存在的不同热系数与印刷电路板上的其它区域的热应力最小化。 印刷电路板包括绝缘层; 形成在所述绝缘层的一个表面上的第一金属线，并且在其一个端部处具有凸起区域和从所述凸起区域整体延伸的突起; 形成在所述绝缘层的另一个表面上并且在其一个端部处具有球形区域的第二金属线; 通过所述绝缘层形成的通孔金属线，以将所述第一和第二金属线彼此连接; 以及形成在绝缘层的上表面和下表面上的阻焊剂，以暴露凸起部分和球状区域。

公开(公告)号：US20130045750A1

公开(公告)日：2013-02-21

申请号：US13337653

申请日：2011-12-27

申请人： Seong Cheol KIM ,  Jung Kyu LEE

发明人： Seong Cheol KIM ,  Jung Kyu LEE

IPC分类号： H04W64/00

CPC分类号： G01S5/14 ,  G01S5/0289 ,  G01S11/06

摘要： A wireless localization technology using efficient multilateration in a wireless sensor network is disclosed. After calculating estimated distances from each of at least three reference nodes to a blind node using received signal strength of wireless signals that the at least three reference nodes received from the blind node, the estimated location of the blind node is obtained through multilateration using the calculated estimated distances. To correct error in the estimated location, the estimated distances are used, and the error correction direction and error correction distance for the estimated location are calculated by applying a largest weight to the reference node closest to the estimated location. The error of the estimated location is corrected by move the estimated location of the blind node by the calculated error correction direction and error correction distance. Calculation for the error correction is very simple and fast.

摘要翻译： 公开了一种在无线传感器网络中使用高效多边测量的无线定位技术。 在使用从盲节点接收到的至少三个参考节点的无线信号的接收信号强度来计算从至少三个参考节点中的每一个到盲节点的估计距离之后，通过使用计算出的 估计距离 为了校正估计位置的误差，使用估计的距离，并且通过对最靠近估计位置的参考节点应用最大权重来计算估计位置的误差校正方向和误差校正距离。 通过将计算的误差校正方向和误差校正距离移动盲节点的估计位置来校正估计位置的误差。 纠错的计算非常简单快捷。

公开(公告)号：US20120049385A1

公开(公告)日：2012-03-01

申请号：US13289365

申请日：2011-11-04

申请人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

发明人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

摘要翻译： 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US20100213596A1

公开(公告)日：2010-08-26

申请号：US12647625

申请日：2009-12-28

申请人： Seong Cheol KIM

发明人： Seong Cheol KIM

IPC分类号： H01L25/07 ,  H01L23/498

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.

摘要翻译： 堆叠包括具有上表面和背表面的下表面的基板，下堆叠组，上堆叠组和连接构件。 下堆叠组附接到基板的上表面，并且包括至少两个半导体芯片，其以面朝上的类型堆叠以形成一个或多个台阶。 上堆叠组布置在下堆叠组上方，并且包括至少两个半导体芯片，其以面朝下的方式堆叠，以形成一个或多个步骤，其方向反映至少一个步骤的方向 下堆叠组。 连接构件将下堆叠组和上堆叠组的半导体芯片电连接到衬底。

公开(公告)号：US20080318361A1

公开(公告)日：2008-12-25

申请号：US11777388

申请日：2007-07-13

申请人： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

发明人： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

IPC分类号： H01L21/44 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

摘要翻译： 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20120129341A1

公开(公告)日：2012-05-24

申请号：US13187845

申请日：2011-07-21

申请人： Seung Hee JO ,  Seong Cheol KIM

发明人： Seung Hee JO ,  Seong Cheol KIM

IPC分类号： H01L21/28 ,  H01L21/311

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.

摘要翻译： 一种用于制造通孔的方法包括在晶片的第一表面上形成第一掩模图案，该第一表面露出晶片的第一表面的一部分，通过将晶体中的杂质注入到晶片的暴露部分中，通过使用 第一掩模图案作为离子注入阻挡层，在包括钝化区的晶片的第一表面上形成蚀刻停止层，在晶片的第二表面上形成第二掩模图案，远离晶片的第一表面，其中 第二掩模图案将晶片的第二表面的一部分暴露在钝化区之间的区域上，并且使用第二掩模图案作为蚀刻掩模通过蚀刻晶片形成通孔。

公开(公告)号：US20110291246A1

公开(公告)日：2011-12-01

申请号：US13096338

申请日：2011-04-28

申请人： Seung Hee JO ,  Seong Cheol KIM

发明人： Seung Hee JO ,  Seong Cheol KIM

IPC分类号： H01L25/07 ,  H01L23/492

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/10165 ,  H01L2224/13009 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81201 ,  H01L2224/81903 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips.

摘要翻译： 半导体封装包括多个堆叠的半导体芯片和填充材料。 堆叠的半导体芯片中的每一个包括具有第一表面和第二表面的半导体衬底，其中在第一表面上形成诸如焊盘的电路图案，以及形成在半导体衬底的第一表面上的第一对准图案， 其中所述第一对准图案由磁性材料形成。 填充材料填充半导体芯片之间的间隙。

公开(公告)号：US20130292842A1

公开(公告)日：2013-11-07

申请号：US13613983

申请日：2012-09-13

申请人： Seong Cheol KIM

发明人： Seong Cheol KIM

IPC分类号： H01L23/538

CPC分类号： H01L23/5384 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

摘要： A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips.

摘要翻译： 堆叠的半导体封装包括多个半导体芯片，每个半导体芯片包括具有一个表面的基板，另一个表面背离该一个表面以及连接一个表面和另一个表面的侧表面，穿过一个表面的通孔硅通孔 衬底的表面和另一个表面，暴露在衬底的侧表面上的修补焊盘以及将穿硅通孔与修补焊盘电连接的布线，多个半导体芯片被堆叠成使得通过硅 半导体芯片的通孔彼此连接; 以及电连接半导体芯片的修补焊盘的互连。