公开(公告)号：US08129826B2

公开(公告)日：2012-03-06

申请号：US12355587

申请日：2009-01-16

申请人： Sang-Wook Park ,  Min-Young Son ,  Hyeong-Seob Kim

发明人： Sang-Wook Park ,  Min-Young Son ,  Hyeong-Seob Kim

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between the semiconductor chips and the support part and including redistribution paths, first signal transmitting units, and second signal transmitting units. The first signal transmitting units transmitting electrical signals generated from the semiconductor chips to the redistribution paths of the redistribution layers, and the second signal transmitting units transmit the electrical signals from the redistribution paths to the external terminals. Therefore, a size and a thickness of the semiconductor package apparatus can be reduced, and processes can be simplified to improve productivity.

摘要翻译： 提供了具有再分配层的半导体封装装置。 该装置包括至少一个或多个半导体芯片，保护半导体芯片的封装部分和支撑半导体芯片的支撑部件。 该设备还包括延伸到包装部分外部的外部端子，重新分配层安装在半导体芯片和支撑部分之间，并且包括再分配路径，第一信号发送单元和第二信号发送单元。 所述第一信号发送单元将从所述半导体芯片生成的电信号发送到所述再分配层的再分配路径，并且所述第二信号发送单元将所述电信号从所述再分配路径发送到所述外部终端。 因此，可以减小半导体封装装置的尺寸和厚度，并且可以简化工艺以提高生产率。

公开(公告)号：US08022517B2

公开(公告)日：2011-09-20

申请号：US12266765

申请日：2008-11-07

申请人： Sung-Hwan Yoon ,  Sang-Wook Park ,  Min-Young Son

发明人： Sung-Hwan Yoon ,  Sang-Wook Park ,  Min-Young Son

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/293 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.

摘要翻译： 半导体芯片封装包括引线框架，绝缘构件，芯片，接合线和密封构件。 引线框架包括多个第一引线和多个第二引线。 第二引线具有芯片粘附区域。 绝缘构件填充芯片粘合区域中的第二引线之间的空间。 芯片设置在绝缘构件的至少一个表面上。 该芯片具有单面接合焊盘。 接合线将引线和接合焊盘电连接。 密封构件覆盖引线框架，绝缘构件，芯片和接合线。 由于第二引线之间的空间填充有绝缘构件，因此可以防止发生空隙。

公开(公告)号：US20090121332A1

公开(公告)日：2009-05-14

申请号：US12266765

申请日：2008-11-07

申请人： Sung-Hwan YOON ,  Sang-Wook Park ,  Min-Young Son

发明人： Sung-Hwan YOON ,  Sang-Wook Park ,  Min-Young Son

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/293 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.

摘要翻译： 半导体芯片封装包括引线框架，绝缘构件，芯片，接合线和密封构件。 引线框架包括多个第一引线和多个第二引线。 第二引线具有芯片粘附区域。 绝缘构件填充芯片粘合区域中的第二引线之间的空间。 芯片设置在绝缘构件的至少一个表面上。 该芯片具有单面接合焊盘。 接合线将引线和接合焊盘电连接。 密封构件覆盖引线框架，绝缘构件，芯片和接合线。 由于第二引线之间的空间填充有绝缘构件，因此可以防止发生空隙。

公开(公告)号：US08552546B2

公开(公告)日：2013-10-08

申请号：US12896091

申请日：2010-10-01

申请人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

发明人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/078 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.

摘要翻译： 提供半导体封装。 半导体封装可以包括具有顺序地堆叠在衬底上的第一半导体芯片的第一半导体封装。 在示例性实施例中，第一半导体芯片可以具有级联布置，其中半导体芯片的第一侧和第二侧限定级联图案。 级联布置可以在第一方向上延伸以限定第一半导体芯片的第一侧和基板之间的空间。 半导体封装还可以包括在半导体芯片的第二面处的至少一个第一连接布线，所述至少一个第一连接布线被配置为将衬底与第一半导体芯片电连接。 此外，半导体封装还可以包括与第一半导体芯片的第一侧相邻的第一填充辅助结构。

公开(公告)号：US08317056B2

公开(公告)日：2012-11-27

申请号：US11777155

申请日：2007-07-12

申请人： Dai-Gil Lee ,  Sang-Wook Park ,  Byung-Chul Kim ,  Seong-su Kim

发明人： Dai-Gil Lee ,  Sang-Wook Park ,  Byung-Chul Kim ,  Seong-su Kim

IPC分类号： F17C1/06 ,  F17C1/00 ,  F17C3/00 ,  F17C13/00

CPC分类号： F17C13/001 ,  F17C2203/0304 ,  F17C2203/0329 ,  F17C2203/0345 ,  F17C2203/035 ,  F17C2203/0358 ,  F17C2203/0643 ,  F17C2209/227 ,  F17C2221/033 ,  F17C2260/011 ,  F17C2270/01 ,  Y10T29/49616

摘要： A structure and method for bonding heat-insulating protection walls of a liquefied natural gas carrier is provided. Each of the heat-insulating protection walls is formed of an insulation foam layer and a fiber-reinforced composite reinforcing sheet attached to a surface of the insulation foam layer. The heat-insulating protection walls are provided in a tank of the liquefied natural gas carrier in a mutually adjoining relationship and bonded to one another at a junction to keep the tank cold. The structure includes a fiber-reinforced composite joint sheet positioned in alignment with the juncture of the heat-insulating protection walls and bonded to the fiber-reinforced composite reinforcing sheet by an adhesive agent and a spacer interposed between the fiber-reinforced composite reinforcing sheet and the fiber-reinforced composite joint sheet for keeping the adhesive agent uniform in thickness.

摘要翻译： 提供了一种用于粘合液化天然气载体的隔热保护壁的结构和方法。 每个绝热保护壁由绝缘泡沫层和附着在绝缘泡沫层的表面上的纤维增强复合增强片形成。 隔热保护壁以相互邻接的关系设置在液化天然气载体的槽中，并且在连接处彼此粘合以保持冷藏。 该结构包括与隔热保护壁的接合部对准的纤维增强复合接合片，并通过粘合剂与间隔开的纤维增强复合增强片粘贴，纤维增强复合增强片与纤维增强复合增强片 用于保持粘合剂厚度均匀的纤维增强复合接合片。

公开(公告)号：US20110079890A1

公开(公告)日：2011-04-07

申请号：US12896091

申请日：2010-10-01

申请人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

发明人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

IPC分类号： H01L25/04

CPC分类号： H01L25/0657 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/078 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.

摘要翻译： 提供半导体封装。 半导体封装可以包括具有顺序地堆叠在衬底上的第一半导体芯片的第一半导体封装。 在示例性实施例中，第一半导体芯片可以具有级联布置，其中半导体芯片的第一侧和第二侧限定级联图案。 级联布置可以在第一方向上延伸以限定第一半导体芯片的第一侧和基板之间的空间。 半导体封装还可以包括在半导体芯片的第二面处的至少一个第一连接布线，所述至少一个第一连接布线被配置为将衬底与第一半导体芯片电连接。 此外，半导体封装还可以包括与第一半导体芯片的第一侧相邻的第一填充辅助结构。

公开(公告)号：US07880291B2

公开(公告)日：2011-02-01

申请号：US12458397

申请日：2009-07-10

申请人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hyung-Gil Baek

发明人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hyung-Gil Baek

IPC分类号： H01L23/48 ,  H01L23/04

CPC分类号： H01L25/105 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.

摘要翻译： 集成电路封装可以包括可以支持集成电路芯片的板。 可以在板的表面上设置柱销。 后引脚可以电连接到集成电路芯片。 可以在板的另一个表面上设置接地引脚。 接地引脚可以电连接到集成电路芯片。

公开(公告)号：US07642636B2

公开(公告)日：2010-01-05

申请号：US11580080

申请日：2006-10-13

申请人： Sang-Wook Park ,  Hyung-Gil Baek

发明人： Sang-Wook Park ,  Hyung-Gil Baek

IPC分类号： H01L23/02

CPC分类号： H01L23/49833 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package may include a plurality of individual packages arranged in a stack. Each individual package may have a circuit substrate disposed on the upper and lower surfaces of a semiconductor chip. Through bonding wires, a lower circuit substrate may be electrically connected to the semiconductor chip, and an upper circuit substrate may be electrically connected to the lower circuit substrate. An upper package in the stack may be mechanically and electrically connected to the upper circuit substrate of a lower package in the stack through conductive bumps. The semiconductor chip may be surrounded by the upper and the lower circuit substrates, and molding resins. The individual packages may have the same conductive bump layout.

摘要翻译： 堆叠包装可以包括以堆叠方式布置的多个单独的包装。 每个单独的封装可以具有设置在半导体芯片的上表面和下表面上的电路基板。 通过接合线，下电路基板可以电连接到半导体芯片，并且上电路基板可以电连接到下电路基板。 堆叠中的上封装可以通过导电凸块机械地和电连接到堆叠中的下封装的上电路基板。 半导体芯片可以被上部和下部电路基板以及模塑树脂包围。 各个封装可能具有相同的导电凸块布局。

公开(公告)号：US07561236B2

公开(公告)日：2009-07-14

申请号：US11642881

申请日：2006-12-21

申请人： Sang-Wook Park ,  Byoung-Ho Lim

发明人： Sang-Wook Park ,  Byoung-Ho Lim

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/1362

摘要： A method of fabricating an array substrate for an IPS mode LCD device includes: forming a common electrode using a double layer of a transparent material layer and an opaque material layer, the common electrode including a first transparent conductive material; forming source and drain electrodes on an ohmic contact layer and a data line connected to the source electrode, the source and drain electrodes being spaced apart from each other; forming a passivation layer on the source and drain electrodes and the data line, the passivation layer including a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode including a second transparent conductive material and being formed in an alternating pattern with the common electrode.

摘要翻译： 制造IPS模式LCD器件的阵列基板的方法包括：使用双层透明材料层和不透明材料层形成公共电极，所述公共电极包括第一透明导电材料; 在欧姆接触层和连接到源电极的数据线上形成源极和漏极，源极和漏极彼此间隔开; 在源极和漏极以及数据线上形成钝化层，钝化层包括暴露漏电极的漏极接触孔; 以及在所述钝化层上形成像素电极，所述像素电极包括第二透明导电材料并以与所述公共电极交替的图案形成。

公开(公告)号：US20090130908A1

公开(公告)日：2009-05-21

申请号：US12318386

申请日：2008-12-29

申请人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

发明人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

IPC分类号： H01R24/00

CPC分类号： H01R12/721 ,  H05K3/305 ,  H05K3/306 ,  H05K2201/0133 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1147 ,  H05K2203/304 ,  Y02P70/613

摘要： In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.