公开(公告)号：US12046297B2

公开(公告)日：2024-07-23

申请号：US17824350

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Peng Wang ,  Jia Li ,  Behrang Bagheri ,  Keyur Payak ,  Bo Lei ,  Long Pham ,  Jun Wan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

公开(公告)号：US20230386580A1

公开(公告)日：2023-11-30

申请号：US17824350

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Peng Wang ,  Jia Li ,  Behrang Bagheri ,  Keyur Payak ,  Bo Lei ,  Long Pham ,  Jun Wan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/32 ,  H01L27/11556

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

公开(公告)号：US11927635B2

公开(公告)日：2024-03-12

申请号：US17731589

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Keyur Payak ,  Naveen Thomas

IPC: H03K17/00 ,  G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  H03K17/693

CPC classification number: G01R31/31905 ,  G01R31/2879 ,  G01R31/31727 ,  G01R31/31924 ,  H03K17/693

Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.

公开(公告)号：US11758718B2

公开(公告)日：2023-09-12

申请号：US17375476

申请日：2021-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Abhijith Prakash ,  Keyur Payak ,  Jiahui Yuan ,  Huai-Yuan Tseng ,  Shinsuke Yada ,  Kazuki Isozumi

IPC: G11C7/00 ,  H10B41/27 ,  H01L29/78 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/7827 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

公开(公告)号：US11335411B1

公开(公告)日：2022-05-17

申请号：US17191315

申请日：2021-03-03

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Keyur Payak ,  Huai-Yuan Tseng

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide multiple channel-to-gate voltages. Current consumption and time are saved compared to applying a multi-level erase voltage to a high capacitance substrate, for example. In one approach, the word line voltage is changed from a positive erase-enable voltage to a negative erase-enable voltage during the multi-level erase pulse. A step size of a next erase pulse can be set to achieve an approximately constant step increase in channel-to-gate voltages of the memory cells.

公开(公告)号：US10998816B1

公开(公告)日：2021-05-04

申请号：US16899428

申请日：2020-06-11

Applicant: SanDisk Technologies LLC

Inventor： Keyur Payak

IPC: H02M3/07

Abstract: Techniques and apparatuses are provided for determining the efficiency of a charge pump. A charge pump is driven during a measurement period without limiting its input current. The driving can include ramping up the output of the charge pump from an initial level to a final level and maintaining the output at the final level. A counter counts a number of clock pulses provided to the charge pump during the measurement period. Using a current mirror which limits the input current, a ratio of the current mirror is determined which results in a similar number of clock pulses during the measurement period. The ratio indicates an efficiency of the charge pump and can be used to set control parameters such as ramp up rate and clock frequency.