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公开(公告)号：US20240321379A1
公开(公告)日：2024-09-26
申请号：US18359816
申请日：2023-07-26
Applicant: SanDisk Technologies LLC
Inventor： Sai Gautham Thoppa , Parth Amin , Long Pham
CPC classification number: G11C29/46 , G11C29/12005 , G11C29/12015
Abstract: Non-volatile memory cells are programmed by raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line; programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period; testing, during the first time period, whether the voltage applied to the selected word line is greater than one or more intermediate voltages; and elongating the first time period during the first time period if the voltage applied to the selected word line is not greater than one or more of the intermediate voltages.
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公开(公告)号：US11955182B2
公开(公告)日：2024-04-09
申请号：US17746616
申请日：2022-05-17
Applicant: SanDisk Technologies LLC
Inventor： Long Pham , Sai Gautham Thoppa
CPC classification number: G11C16/102 , G11C16/26 , G11C16/32 , G11C16/3404
Abstract: Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.
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公开(公告)号：US10529435B2
公开(公告)日：2020-01-07
申请号：US15863404
申请日：2018-01-05
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Deepanshu Dutta , Long Pham
Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.
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Patent Agency Ranking
公开(公告)号：US20230386580A1
公开(公告)日：2023-11-30
申请号：US17824350
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Peng Wang , Jia Li , Behrang Bagheri , Keyur Payak , Bo Lei , Long Pham , Jun Wan
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/32 , H01L27/11556
Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
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公开(公告)号：US20180210661A1
公开(公告)日：2018-07-26
申请号：US15933365
申请日：2018-03-22
Applicant: SanDisk Technologies LLC
Inventor： Jea Hyun , James Peterson , Long Pham , John Strasser , Hairong Sun , Kapil Verma
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/067 , G06F3/0688
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. An integrated circuit chip comprising non-volatile memory, the integrated circuit chip configured to, determine a number of portions into which a storage operation is to be split; pause execution of the storage operation from within the integrated circuit chip according to the determined number of portions; execute one or more other storage operations on the integrated circuit chip while the storage operation is paused, each of the one or more other storage operations having a shorter duration than the storage operation; and continue the paused storage operation in response to a trigger.
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公开(公告)号：US12046297B2
公开(公告)日：2024-07-23
申请号：US17824350
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Peng Wang , Jia Li , Behrang Bagheri , Keyur Payak , Bo Lei , Long Pham , Jun Wan
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/32 , H10B41/27 , H10B43/27
Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
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公开(公告)号：US20190214100A1
公开(公告)日：2019-07-11
申请号：US15863404
申请日：2018-01-05
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Deepanshu Dutta , Long Pham
Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.
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公开(公告)号：US10089021B2
公开(公告)日：2018-10-02
申请号：US15933365
申请日：2018-03-22
Applicant: SanDisk Technologies LLC
Inventor： Jea Hyun , James Peterson , Long Pham , John Strasser , Hairong Sun , Kapil Verma
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. An integrated circuit chip comprising non-volatile memory, the integrated circuit chip configured to, determine a number of portions into which a storage operation is to be split; pause execution of the storage operation from within the integrated circuit chip according to the determined number of portions; execute one or more other storage operations on the integrated circuit chip while the storage operation is paused, each of the one or more other storage operations having a shorter duration than the storage operation; and continue the paused storage operation in response to a trigger.
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