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    Dynamic read table generation
    1.
    发明授权
    Dynamic read table generation 有权

    公开(公告)号：US10558381B2

    公开(公告)日：2020-02-11

    申请号：US15381104

    申请日：2016-12-16

    Applicant: SanDisk Technologies LLC

    Inventor： Henry Chin ,  Sateesh Desireddi ,  Dana Lee ,  Ashwin D T ,  Harshul Gupta ,  Parth Amin ,  Jia Li

    IPC: G06F3/06

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

    NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING
    2.
    发明公开
    NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING 审中-公开

    公开(公告)号：US20240290412A1

    公开(公告)日：2024-08-29

    申请号：US18346339

    申请日：2023-07-03

    Applicant: SanDisk Technologies LLC

    Inventor： Sai Gautham Thoppa ,  Parth Amin ,  Anubhav Khandelwal

    IPC: G11C29/44 ,  G06F12/1009 ,  G11C29/12

    CPC classification number: G11C29/44 ,  G06F12/1009 ,  G11C29/12005 ,  G11C2029/1202

    Abstract: As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the defect tests into the erase process, when biasing the memory array for the post-erase defect tests different ramp rates can be used. In particular, faster ramp rates for bias levels, such those applied to the word lines of the block, are used for the post-erase tests than are used for the same bias level when performing the standard read, program verify, or read verify operations.

    ?READ AFTER ERASE? METHOD FOR CATCHING SINGLE WORD LINE ?SLOW TO ERASE? SIGNATURE IN NON-VOLATILE MEMORY ST
    3.
    发明申请
    ?READ AFTER ERASE? METHOD FOR CATCHING SINGLE WORD LINE ?SLOW TO ERASE? SIGNATURE IN NON-VOLATILE MEMORY ST 有权

    公开(公告)号：US20220415413A1

    公开(公告)日：2022-12-29

    申请号：US17356823

    申请日：2021-06-24

    Applicant: SanDisk Technologies LLC

    Inventor： Parth Amin ,  Anubhav Khandelwal

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26

    Abstract: A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.

    System and methods for programming nonvolatile memory having partial select gate drains
    4.
    发明授权
    System and methods for programming nonvolatile memory having partial select gate drains 有权

    公开(公告)号：US11581049B2

    公开(公告)日：2023-02-14

    申请号：US17335909

    申请日：2021-06-01

    Applicant: SanDisk Technologies LLC

    Inventor： Kazuki Isozumi ,  Parth Amin ,  Sayako Nagamine ,  Anubhav Khandelwal

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/52 ,  G11C16/08 ,  G11C29/12

    Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

    Programming techniques for memory devices having partial drain-side select gates
    5.
    发明授权
    Programming techniques for memory devices having partial drain-side select gates 有权

    公开(公告)号：US11562798B2

    公开(公告)日：2023-01-24

    申请号：US17348261

    申请日：2021-06-15

    Applicant: SanDisk Technologies LLC

    Inventor： Parth Amin ,  Anubhav Khandelwal

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34 ,  G11C16/24 ,  G11C16/30 ,  G11C16/26

    Abstract: The programming techniques include the step of providing a memory device that includes a plurality of memory cells that are divided into at least two groups including a first group and a second group. The first group includes memory cells that are coupled to full select gate drains (SGDs), and the second group includes memory cells that are coupled to partial SGDs. The method continues with the step of applying a programming voltage to a selected word line that includes at least one memory cell of the first group and at least one memory cell of the second group. Simultaneous to the application of the programming voltage, the method continues with applying voltages to bit lines coupled to memory cells. The voltages being determined based on if the memory cells are of the first group or are of the second group.

    MEMORY APPARATUS AND METHOD OF OPERATION USING DYNAMIC MAX PROGRAM LOOP
    6.
    发明申请
    MEMORY APPARATUS AND METHOD OF OPERATION USING DYNAMIC MAX PROGRAM LOOP 有权

    公开(公告)号：US20220399058A1

    公开(公告)日：2022-12-15

    申请号：US17343179

    申请日：2021-06-09

    Applicant: SanDisk Technologies LLC

    Inventor： Parth Amin ,  Anubhav Khandelwal

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C11/56

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage corresponding to memory states. A control circuit is configured to program the memory cells to reach one of a plurality of verify levels each corresponding the memory states using a series of voltage pulses applied to the word lines during a program operation. The control circuit determines an intermediate quantity of the series of voltage pulses necessary for the memory cells associated with a selected one of the memory states to reach the one of the plurality of verify levels corresponding to the selected one of the memory states. The control circuit ends the program operation after a maximum allowable quantity of the series of voltage pulses are utilized. The maximum allowable quantity is selected based on the intermediate quantity.

    SYSTEM AND METHODS FOR PROGRAMMING NONVOLATILE MEMORY HAVING PARTIAL SELECT GATE DRAINS
    7.
    发明申请
    SYSTEM AND METHODS FOR PROGRAMMING NONVOLATILE MEMORY HAVING PARTIAL SELECT GATE DRAINS 有权

    公开(公告)号：US20220383967A1

    公开(公告)日：2022-12-01

    申请号：US17335909

    申请日：2021-06-01

    Applicant: SanDisk Technologies LLC

    Inventor： Kazuki Isozumi ,  Parth Amin ,  Sayako Nagamine ,  Anubhav Khandelwal

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/12 ,  G11C16/08 ,  G11C29/52

    Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

    VERA DETECTION METHOD TO CATCH ERASE FAIL
    8.
    发明公开
    VERA DETECTION METHOD TO CATCH ERASE FAIL 审中-公开

    公开(公告)号：US20240161858A1

    公开(公告)日：2024-05-16

    申请号：US18356786

    申请日：2023-07-21

    Applicant: SanDisk Technologies LLC

    Inventor： Parth Amin ,  Sai Gautham Thoppa ,  Anubhav Khandelwal

    IPC: G11C29/46 ,  G11C16/14 ,  G11C29/12

    CPC classification number: G11C29/46 ,  G11C16/14 ,  G11C29/1201

    Abstract: Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

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