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1.发明授权公开(公告)号：US12190963B2
公开(公告)日：2025-01-07
申请号：US18235838
申请日：2023-08-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Se-Hwan Park , Wan-Dong Kim
IPC: G11C11/34 , G06F13/16 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/34 , G11C16/14 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
Abstract: A memory device may include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block may include first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device mat be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
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公开(公告)号：US11462270B2
公开(公告)日：2022-10-04
申请号：US17010898
申请日：2020-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Se-Hwan Park
Abstract: Nonvolatile memory device includes memory cell region including first metal pad, peripheral circuit region including second metal pad, memory cell array, input current generator, operation cell array and analog-to-digital converter. Peripheral circuit region is vertically connected by first and second metal pads. Memory cell array in memory cell region includes NAND strings storing multiplicand data, wherein first ends of NAND strings are connected to bitlines and second ends of NAND strings output multiplication bits corresponding to bitwise multiplication of multiplicand data stored in NAND strings and multiplier data loaded on bitlines. Input current generator generates input currents. Operation cell array in memory cell region includes switching transistors. Gate electrodes of switching transistors are connected to second ends of NAND strings. Switching transistors selectively sum input currents based on multiplication bits to provide output currents. Analog-to-digital converter converts output currents to digital values.
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3.发明申请公开(公告)号：US20190074065A1
公开(公告)日：2019-03-07
申请号：US16004770
申请日：2018-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Se-Hwan Park , Wan-Dong Kim
Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
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4.发明授权公开(公告)号：US11804268B2
公开(公告)日：2023-10-31
申请号：US17525934
申请日：2021-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Se-Hwan Park , Wan-Dong Kim
IPC: G11C11/34 , G11C16/24 , G11C16/34 , G06F13/16 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C11/56 , G11C16/14 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC classification number: G11C16/24 , G06F13/1668 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3418 , G06F2213/0024 , G11C16/14 , G11C2211/5648 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
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公开(公告)号：US11164632B2
公开(公告)日：2021-11-02
申请号：US17187781
申请日：2021-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Se-Hwan Park
Abstract: A nonvolatile memory device includes a memory cell array, an input current generator, an operation cell array and an analog-to-digital converter. The memory cell array includes NAND strings storing multiplicand data, wherein first ends of the NAND strings are connected to bitlines and second ends of the NAND strings output multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the NAND strings and multiplier data loaded on the bitlines. The input current generator generates input currents. The operation cell array includes switching transistors. Gate electrodes of the switching transistors are connected to the second ends of the NAND strings. The switching transistors selectively sum the input currents based on the multiplication bits to output the output currents. The analog-to-digital converter converts the output currents to digital values.
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Patent Agency Ranking
公开(公告)号：US10971230B2
公开(公告)日：2021-04-06
申请号：US16550195
申请日：2019-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Se-Hwan Park
Abstract: A nonvolatile memory device includes a memory cell array, an input current generator, an operation cell array and an analog-to-digital converter. The memory cell array includes NAND strings storing multiplicand data, wherein first ends of the NAND strings are connected to bitlines and second ends of the NAND strings output multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the NAND strings and multiplier data loaded on the bitlines. The input current generator generates input currents. The operation cell array includes switching transistors. Gate electrodes of the switching transistors are connected to the second ends of the NAND strings. The switching transistors selectively sum the input currents based on the multiplication bits to output the output currents. The analog-to-digital converter converts the output currents to digital values.
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公开(公告)号：US20190156896A1
公开(公告)日：2019-05-23
申请号：US16043964
申请日：2018-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Yoon Park , Wan-Dong Kim , Seung-Bum Kim , Deok-Woo Lee , You-Se Kim , Se-Hwan Park , Jin-Woo Park
CPC classification number: G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/32 , G11C16/3445 , G11C29/52
Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.
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8.发明授权公开(公告)号：US09389700B2
公开(公告)日：2016-07-12
申请号：US14859762
申请日：2015-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Se-Hwan Park , Keun-Ho Shin , Woo-Jei Choi
IPC: G06F3/041 , G06F3/023 , G06F3/0484 , G06F3/0488 , G06F3/0489
CPC classification number: G06F3/0236 , G06F3/0237 , G06F3/0412 , G06F3/04845 , G06F3/04886 , G06F3/04895 , G06F2203/04803 , G06F2203/04805
Abstract: An apparatus and method for inputting a character on a touch keyboard in a terminal are provided. A touch screen displays a basic key set and an extended key set. The basic key set includes consonant keys and the extended key set includes character keys corresponding to characters combinable with a consonant corresponding to a consonant key input from the basic key set. The touch screen displays the extended key set, upon input of the consonant key from the basic key set and receiving at least one character from the basic key set and the extended key set.
Abstract translation: 提供一种用于在终端中的触摸键盘上输入字符的装置和方法。 触摸屏显示基本密钥集和扩展密钥集。 基本键集包括辅音键，并且扩展键组包括对应于与从与基本键组输入的辅音键对应的辅音可组合的字符的字符键。 当从基本密钥组输入辅音键并从基本密钥组和扩展密钥组接收至少一个字符时，触摸屏显示扩展密钥集。
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9.发明授权Apparatus and method for scaling layout of application in image display device 有权用于在图像显示装置中缩放应用的布局的装置和方法公开(公告)号：US09275433B2
公开(公告)日：2016-03-01
申请号：US13737258
申请日：2013-01-09
Applicant: Samsung Electronics Co. Ltd.
Inventor： So-Hyun Kim , Seung-Gyun Kim , Haitzler Carsten , Sun-Gi Hong , Du-Il Kim , Se-Hwan Park , Jang-Hyun Yoon , Sang-Jin Lee , Seok-Jae Jeong , Jin-Hee Choi
IPC: G09G5/00 , G06T3/40 , G06F3/048 , G06T11/60 , G06F3/0481
CPC classification number: G06T3/40 , G06F3/048 , G06F3/0481 , G06F2203/04806 , G06T11/60 , G09G2340/0407 , G09G2340/0414
Abstract: An apparatus and method for scaling a layout of an application in an image display device are provided. The method for scaling includes generating a scaling variable considering a distance between the image display device and a user, and scaling a layout of an application using the scaling variable.
Abstract translation: 提供了一种用于缩放图像显示装置中的应用的布局的装置和方法。 缩放的方法包括考虑图像显示设备和用户之间的距离来生成缩放变量，以及使用缩放变量缩放应用的布局。
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10.发明授权公开(公告)号：US11276471B2
公开(公告)日：2022-03-15
申请号：US17207657
申请日：2021-03-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Se-Hwan Park , Wan-Dong Kim
IPC: G11C11/34 , G11C16/24 , G11C11/56 , G11C16/34 , G06F13/16 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/14 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
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