公开(公告)号：US20190156896A1

公开(公告)日：2019-05-23

申请号：US16043964

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yoon Park ,  Wan-Dong Kim ,  Seung-Bum Kim ,  Deok-Woo Lee ,  You-Se Kim ,  Se-Hwan Park ,  Jin-Woo Park

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3445 ,  G11C29/52

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

公开(公告)号：US12125544B2

公开(公告)日：2024-10-22

申请号：US17871358

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： You-Se Kim ,  Sang-Wan Nam ,  Kee Ho Jung

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24

Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.