公开(公告)号：US20220139799A1

公开(公告)日：2022-05-05

申请号：US17508483

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Jung ,  Sanguk Han ,  Yoonha Jung

IPC: H01L23/373 ,  H01L23/498 ,  H01L25/18 ,  H05K1/18 ,  H05K1/02

Abstract: A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.

公开(公告)号：US09425156B2

公开(公告)日：2016-08-23

申请号：US14283828

申请日：2014-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Abstract translation: 半导体封装包括其中具有通孔的第一板，设置在第一板的第一表面上的至少一个互连层，以及至少一个半导体芯片，该半导体芯片设置在由通孔限定的空间中的至少一个互连层上 并且电连接到所述至少一个互连层。 所述封装还包括设置在所述至少一个半导体芯片上的第二板和所述第一板的与所述第一表面相对的一侧上的所述第一板的第二表面，以及设置在所述第一板的第二表面上的至少一个导电垫 并且电连接到所述至少一个互连层。

公开(公告)号：US11824076B2

公开(公告)日：2023-11-21

申请号：US17731022

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Chungsun Lee ,  Yoonha Jung ,  Chajea Jo

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

CPC classification number: H01L27/14634 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/32 ,  H01L27/1469 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US11335719B2

公开(公告)日：2022-05-17

申请号：US16802683

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Chungsun Lee ,  Yoonha Jung ,  Chajea Jo

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US10211159B2

公开(公告)日：2019-02-19

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US11842945B2

公开(公告)日：2023-12-12

申请号：US17508483

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Jung ,  Sanguk Han ,  Yoonha Jung

IPC: H01L25/18 ,  H01L23/373 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/00 ,  H05K1/14

CPC classification number: H01L23/3735 ,  H01L23/3733 ,  H01L23/3737 ,  H01L23/4985 ,  H01L25/18 ,  H05K1/0204 ,  H05K1/189 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204 ,  H05K1/147 ,  H05K2201/10128

Abstract: A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.

公开(公告)号：US10825776B2

公开(公告)日：2020-11-03

申请号：US16240174

申请日：2019-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US09659852B2

公开(公告)日：2017-05-23

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk Kim ,  HyunJong Moon ,  Tai-Hyun Eum ,  Heeseok Lee ,  Keung Beum Kim ,  Yonghoon Kim ,  Yoonha Jung ,  Seung-Yong Cha

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.