公开(公告)号：US20170069369A1

公开(公告)日：2017-03-09

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108 ,  H01L25/065

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

Abstract translation: 半导体存储器件包括具有用于管芯端接的第一终端电阻器和第二存储器管芯的第一存储器管芯，具有用于管芯端接的第二终端电阻器并形成在第一存储器管芯上。 第一和第二存储器管芯中的每一个具有中心焊盘类型并且基于多级结构进行操作。 当访问第一存储器管芯时，第二终端电阻器连接到第二存储管芯，并且当访问第二存储器管芯时，第一终端电阻器连接到第一存储器管芯。

公开(公告)号：US09721644B2

公开(公告)日：2017-08-01

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C5/02 ,  G11C11/4093 ,  H01L27/108 ,  H01L25/065 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

公开(公告)号：US09830973B2

公开(公告)日：2017-11-28

申请号：US15639073

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C5/02 ,  G11C11/4093 ,  H01L27/108 ,  H01L25/065 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

公开(公告)号：US09659852B2

公开(公告)日：2017-05-23

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk Kim ,  HyunJong Moon ,  Tai-Hyun Eum ,  Heeseok Lee ,  Keung Beum Kim ,  Yonghoon Kim ,  Yoonha Jung ,  Seung-Yong Cha

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

公开(公告)号：US09799591B2

公开(公告)日：2017-10-24

申请号：US14825831

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yong Cha ,  Keung Beum Kim ,  Yonghoon Kim ,  HyunJong Moon ,  Heeseok Lee

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/367 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/49827 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1713 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

公开(公告)号：US20170301392A1

公开(公告)日：2017-10-19

申请号：US15639073

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C11/4093 ,  G11C11/408 ,  G11C7/10 ,  H01L25/065 ,  H01L27/108 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.