公开(公告)号：US09748263B2

公开(公告)日：2017-08-29

申请号：US15097485

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-chul Jang ,  Hong-soo Kim ,  Tae-keun Cho

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/08 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L29/788

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/222 ,  H01L27/249 ,  H01L29/7889 ,  H01L43/08 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

Abstract: A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.

公开(公告)号：US20170012052A1

公开(公告)日：2017-01-12

申请号：US15097485

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： WON-CHUL JANG ,  Hong-soo Kim ,  Tae-keun Cho

IPC: H01L27/115 ,  H01L23/522 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L29/788 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L23/528 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/222 ,  H01L27/249 ,  H01L29/7889 ,  H01L43/08 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

Abstract: A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.

Abstract translation: 半导体存储器件包括沿第一方向延伸的串选择线，连接到串选择线的垂直柱，串选择线上的子互连，通过子互连连接到垂直柱的位线，以及连接 与位线的子互连。 字符串选择行包括在第二方向交替布置的奇数和偶数字符串选择行。 子互连每个连接一对垂直柱，其分别连接到奇数串选择线之一和彼此相邻的偶数串选择线之一。 每个上部接触插塞位于一个子互连和一个位线之间。 每个上接触插塞被布置成更靠近由相互连接的一对垂直柱连接的相邻串选择线的一个串选择线。