公开(公告)号：US09748263B2

公开(公告)日：2017-08-29

申请号：US15097485

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-chul Jang ,  Hong-soo Kim ,  Tae-keun Cho

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/08 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L29/788

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/222 ,  H01L27/249 ,  H01L29/7889 ,  H01L43/08 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

Abstract: A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.