公开(公告)号：US12107122B2

公开(公告)日：2024-10-01

申请号：US18307074

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US20230335558A1

公开(公告)日：2023-10-19

申请号：US18117891

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor device includes: an active pattern extending in a first direction, parallel to an upper surface of a substrate, on the substrate; a gate structure extending in a second direction, intersecting the first direction, on the active pattern; a source/drain region disposed in a region, adjacent to the gate structure, on the active pattern; an interlayer insulating layer covering the gate structure and the source/drain region; and a contact structure penetrating through the interlayer insulating layer and contacting the source/drain region. The contact structure may include a contact plug, an insulating liner surrounding a sidewall of the contact plug, and a conductive barrier layer disposed between the insulating liner and the contact plug and on a bottom surface of the contact plug. The conductive barrier layer may have a barrier extension portion extending downwardly from a lower end of the insulating liner.

公开(公告)号：US12191373B2

公开(公告)日：2025-01-07

申请号：US17526634

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo Kang ,  Sungsoo Kim ,  Sunki Min ,  Iksoo Kim ,  Donghyun Roh

IPC: H01L29/49 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

公开(公告)号：US20230261047A1

公开(公告)日：2023-08-17

申请号：US18307074

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L27/088 ,  H01L27/092 ,  H01L21/823878 ,  H01L21/823481

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US11670676B2

公开(公告)日：2023-06-06

申请号：US17379051

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US11239120B2

公开(公告)日：2022-02-01

申请号：US16793997

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunki Min ,  Donghyun Roh

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/764

Abstract: A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.

公开(公告)号：US20210098592A1

公开(公告)日：2021-04-01

申请号：US16837329

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo Kang ,  Sungsoo Kim ,  Sunki Min ,  Iksoo Kim ,  Donghyun Roh

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction on the substrate, the gate structure including a gate electrode, a gate capping layer on the gate electrode, and a plurality of spacers on side surfaces of the gate electrode; source/drain regions on the active region on at least one side of the gate structure; a first insulating layer and a second insulating layer on the source/drain regions on at least one side of the gate structure; and contact plugs on the source/drain regions and penetrating the first and second insulating layers. The plurality of spacers include a first spacer on the side surfaces of the gate electrode, an air-gap spacer on an external side surface of the first spacer, and a second spacer on an external side surface of the air-gap spacer An upper portion of the second spacer is bent towards an upper portion of the first spacer and is configured to cap the air-gap spacer.

公开(公告)号：US20220077301A1

公开(公告)日：2022-03-10

申请号：US17526634

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo Kang ,  Sungsoo Kim ,  Sunki Min ,  Iksoo Kim ,  Donghyun Roh

IPC: H01L29/49 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction on the substrate, the gate structure including a gate electrode, a gate capping layer on the gate electrode, and a plurality of spacers on side surfaces of the gate electrode; source/drain regions on the active region on at least one side of the gate structure; a first insulating layer and a second insulating layer on the source/drain regions on at least one side of the gate structure; and contact plugs on the source/drain regions and penetrating the first and second insulating layers. The plurality of spacers include a first spacer on the side surfaces of the gate electrode, an air-gap spacer on an external side surface of the first spacer, and a second spacer on an external side surface of the air-gap spacer. An upper portion of the second spacer is bent towards an upper portion of the first spacer and is configured to cap the air-gap spacer.

公开(公告)号：US20200185280A1

公开(公告)日：2020-06-11

申请号：US16793997

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunki Min ,  Donghyun ROH

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L21/764 ,  H01L21/762

Abstract: A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.

公开(公告)号：US11776857B2

公开(公告)日：2023-10-03

申请号：US17567403

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunki Min ,  Donghyun Roh

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/764 ,  H01L21/76229 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0924 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/41791

Abstract: A method for manufacturing a semiconductor device includes forming a first active fin and a second active fin on a first active region and a second active region of a substrate, respectively, forming a device isolation layer to cover sidewalls of lower portions of the first active fin and the second active fin, forming a first liner layer and a second liner layer to cover upper portions of the first active fin and the second active fin, respectively, forming a first gate electrode and a second gate electrode on the first active fin and the second active fin, respectively, and forming a first source/drain region and a second source/drain region on the first active fin and the second active fin, respectively. The first liner layer includes a different material from a material of the second liner layer.