公开(公告)号：US20190333914A1

公开(公告)日：2019-10-31

申请号：US16194468

申请日：2018-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki MIN

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US20230369330A1

公开(公告)日：2023-11-16

申请号：US18165563

申请日：2023-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki MIN ,  Sang Hyun PARK

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823878

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a substrate, and a second active pattern extending in the first direction on the substrate, the second active pattern spaced apart from the first active pattern in a second direction. The device includes a field insulating film between the first active pattern and the second active pattern on the substrate, a first gate electrode intersecting the first active pattern on the substrate, a second gate electrode intersecting the second active pattern on the substrate, and a gate separation structure on the field insulating film. The gate separation structure separates the first gate electrode and the second gate electrode from each other, the gate separation structure includes a plurality of first sub-insulating films and at least one second sub-insulating film, and the at least one second sub-insulating film is between the first sub-insulating films.

公开(公告)号：US20230207561A1

公开(公告)日：2023-06-29

申请号：US18117594

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ki MIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L29/42372 ,  H01L21/76224

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US20240203988A1

公开(公告)日：2024-06-20

申请号：US18591687

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki MIN

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L29/42372

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

公开(公告)号：US20240128332A1

公开(公告)日：2024-04-18

申请号：US18350614

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Shin JANG ,  Jong Min BAEK ,  Sun Ki MIN ,  Na rae OH

IPC: H01L29/417 ,  H01L23/48 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41725 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.

公开(公告)号：US20180138174A1

公开(公告)日：2018-05-17

申请号：US15807012

申请日：2017-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki MIN ,  Sang Koo Kang ,  Koung Min Ryu ,  Gi Gwan Park

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.

公开(公告)号：US20230070925A1

公开(公告)日：2023-03-09

申请号：US17706815

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Sun Ki MIN ,  Na Rae OH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction and spaced apart from the first active pattern in a second direction on the substrate; a field insulating layer between the first active pattern and the second active pattern on the substrate; a first gate electrode on the first active pattern; a second gate electrode on the second active pattern; and a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer, wherein a width of the gate isolation structure in the second direction varies in a downward direction from the upper isolation pattern.

公开(公告)号：US20220223526A1

公开(公告)日：2022-07-14

申请号：US17489164

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Ki MIN

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device comprises a gate structure including a gate electrode, on a substrate, a source/drain pattern disposed on a side surface of the gate electrode, on the substrate, a first interlayer insulating layer on the gate structure, a first via plug disposed in the first interlayer insulating layer and connected to the source/drain pattern, an etch stop structure layer including first to third etch stop layers sequentially stacked, on the first interlayer insulating layer, such that the second etch stop layer is between the first etch stop layer and the third etch stop layer, a second interlayer insulating layer contacting the etch stop structure layer, on the etch stop structure layer, such that the etch stop structure layer is between the first interlayer insulating layer and the second interlayer insulating layer, and a wire line disposed in the second interlayer insulating layer and contacting the first via plug. The first etch stop layer contacts a top surface of the first interlayer insulating layer, and the third etch stop layer is a continuously-formed layer that includes a first horizontal portion extending along a top surface of the first interlayer insulating layer, and a first vertical portion protruding from the first horizontal portion of the third etch stop layer in a thickness direction of the substrate.

公开(公告)号：US20210104521A1

公开(公告)日：2021-04-08

申请号：US17102659

申请日：2020-11-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ki MIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/762

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.