公开(公告)号：US20200373402A1

公开(公告)日：2020-11-26

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Seung Min SONG ,  Soo Jin JEONG ,  Dong Il BAE ,  Bong Seok SUH

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US20240222374A1

公开(公告)日：2024-07-04

申请号：US18457313

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Gwon KIM ,  Myung Gil KANG ,  Soo Jin JEONG ,  Dong Won KIM ,  Beom Jin PARK ,  Hong Seon YANG

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.

公开(公告)号：US20240006497A1

公开(公告)日：2024-01-04

申请号：US18138877

申请日：2023-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Jin JEONG ,  Myung Gil KANG ,  Tae Gon KIM ,  Dong Won KIM ,  Ju Ri LEE

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66545

Abstract: A semiconductor device includes an active pattern having a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in a first direction; first and second structures disposed on the lower pattern, wherein the first and second structures are arranged and spaced apart from each other in a second direction; a source/drain recess defined between first and second gate structures; and a source/drain pattern filling the source/drain recess, wherein the source/drain pattern includes a stacking fault spaced apart from the lower pattern.

公开(公告)号：US20220208967A1

公开(公告)日：2022-06-30

申请号：US17388225

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Dong KO ,  Woo Cheol SHIN ,  Soo Jin JEONG

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, first and second nanosheets stacked on the active pattern to be spaced apart from each other in a vertical direction, a gate electrode that extends in a second direction the active pattern, the gate electrode surrounding each of the first and second nanosheets, a source/drain region on at least one side of the gate electrode, and inner spacers between the gate electrode and the source/drain region, the inner spacers including a first inner spacer between the active pattern and the first nanosheet, and a second inner spacer between the first nanosheet and the second nanosheet, the second inner spacer having a first portion adjacent to the first nanosheet, and a second portion adjacent to the second nanosheet, the first portion being wider than the second portion.

公开(公告)号：US20220231127A1

公开(公告)日：2022-07-21

申请号：US17715273

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Seung Min SONG ,  Soo Jin JEONG ,  Dong Il BAE ,  Bong Seok SUH

IPC: H01L29/08 ,  H01L29/04 ,  H01L29/786

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

公开(公告)号：US20210399108A1

公开(公告)日：2021-12-23

申请号：US17467660

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Seung Min SONG ,  Soo Jin JEONG ,  Dong Il BAE ,  Bong Seok SUH

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L27/12

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.