公开(公告)号：US20240405104A1

公开(公告)日：2024-12-05

申请号：US18648580

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Gwon KIM ,  Myung Gil KANG ,  Jin Kyu KIM ,  Dong Won KIM ,  Beom Jin PARK

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.

公开(公告)号：US20240222374A1

公开(公告)日：2024-07-04

申请号：US18457313

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Gwon KIM ,  Myung Gil KANG ,  Soo Jin JEONG ,  Dong Won KIM ,  Beom Jin PARK ,  Hong Seon YANG

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.

公开(公告)号：US20240186392A1

公开(公告)日：2024-06-06

申请号：US18062116

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin PARK ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/775

Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

公开(公告)号：US20230170386A1

公开(公告)日：2023-06-01

申请号：US17888639

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Jin LEE ,  Beom Jin PARK ,  Myoung Sun LEE ,  Keun Hwi CHO ,  Dong Won KIM

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/775 ,  H01L29/6656 ,  H01L29/78696

Abstract: A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.

公开(公告)号：US20220130865A1

公开(公告)日：2022-04-28

申请号：US17336785

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin PARK ,  Myung Gil KANG ,  Dong Won KIM ,  Keun Hwi CHO

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOT substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.