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    Hardware architecture for acceleration of computer vision and imaging processing
    2.
    发明授权
    Hardware architecture for acceleration of computer vision and imaging processing 有权

    公开(公告)号：US10055807B2

    公开(公告)日：2018-08-21

    申请号：US15059175

    申请日：2016-03-02

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Seungjin Lee ,  Seok-Jun Lee

    IPC: G06T1/60 ,  G06T1/20 ,  G09G5/36

    CPC classification number: G06T1/20 ,  G06F9/544 ,  G06T1/60

    Abstract: An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.

    Image sensor and operation method thereof
    4.
    发明授权
    Image sensor and operation method thereof 有权

    公开(公告)号：US11323639B2

    公开(公告)日：2022-05-03

    申请号：US16999586

    申请日：2020-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soonik Cho ,  Minji Hwang ,  Seungjin Lee

    IPC: H04N5/341 ,  H04N5/374

    Abstract: An image sensor and an operation method of the image sensor are disclosed. The image sensor includes a pixel array and a row driver. The pixel array includes a first pixel and a second pixel. Each of the first pixel and the second pixel includes at least one photosensitive element and a switching element configured to transfer charges generated by the at least one photosensitive element to a floating diffusion node. The first pixel and the second pixel are connected to a same column line. The row driver is configured to provide a clamping control signal to the switching element in the first pixel. The clamping control signal transits from a first level to a second level that is less than the first level, during a read period of the second pixel.

    Image sensors including shielding structures
    5.
    发明授权
    Image sensors including shielding structures 有权

    公开(公告)号：US10313616B2

    公开(公告)日：2019-06-04

    申请号：US15434605

    申请日：2017-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yunhwan Jung ,  Sunyool Kang ,  Kyoungmin Koh ,  Seungjin Lee

    IPC: H04N5/335 ,  H04N5/357 ,  H04N5/374 ,  H04N5/378 ,  H04N9/04

    Abstract: An image sensor includes first pixels and second pixels arranged in alternating order along a first direction, first output lines extending in a second direction that is perpendicular to the first direction and respectively connected to the first pixels, second output lines extending in the second direction and respectively connected to the second pixels, first analog circuit blocks and second analog circuit blocks arranged in alternating order along the first direction, and shielding structures disposed each between adjacent ones of the first and second analog circuit blocks. Each of the first analog circuit blocks includes a plurality of first analog circuits respectively connected to the first output lines. Each of the second analog circuit blocks includes a plurality of second analog circuits respectively connected to the second output lines.

    HARDWARE ARCHITECTURE FOR ACCELERATION OF COMPUTER VISION AND IMAGING PROCESSING
    6.
    发明申请
    HARDWARE ARCHITECTURE FOR ACCELERATION OF COMPUTER VISION AND IMAGING PROCESSING 审中-公开

    公开(公告)号：US20170256016A1

    公开(公告)日：2017-09-07

    申请号：US15059175

    申请日：2016-03-02

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Seungjin Lee ,  Seok-Jun Lee

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60

    Abstract: An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.

    Flux dotting tool
    8.
    发明授权
    Flux dotting tool 有权

    公开(公告)号：US11818850B2

    公开(公告)日：2023-11-14

    申请号：US17582590

    申请日：2022-01-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjin Lee ,  Jongbeom Park

    IPC: B23K1/00 ,  H05K3/40 ,  B23K1/20

    CPC classification number: H05K3/4007 ,  B23K1/203 ,  H05K2203/0126

    Abstract: A flux dotting tool is provided that includes: a housing having an internal space and a plurality of through-holes extending from the internal space to an outside of the housing; a plurality of flux pins disposed in the internal space to correspond to the plurality of through-holes, respectively, wherein each of the plurality of flux pins includes a flux holding portion extending in a first direction and that is exposed to the outside of the housing, and a flux blocking structure protruding in a second direction, perpendicular to the first direction, from a side surface of the flux holding portion, and the flux blocking structure is configured to limit a flux wetting region; and an elastic structure disposed on the plurality of flux pins in the internal space and configured to impart elastic force in the first direction.

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