OPERATOR IMPLEMENTATIONS FOR QUANTUM COMPUTATION

    公开(公告)号:US20240281693A1

    公开(公告)日:2024-08-22

    申请号:US18034444

    申请日:2021-10-19

    CPC classification number: G06N10/60 G06F17/14 G06N10/20 G06N10/40

    Abstract: A computer-implemented method and system for implementing a n-fold fermionic excitation generator using linear combination of directly differentiable operators on a quantum computer. Computer-readable data is generated and stored which when executed on the quantum computer, causes a quantum circuit of the quantum computer to execute repeatedly to perform a sequence of operations that implements the unitary (I) generated by a fermionic n-fold excitation operator G. The Gradient with respect to the angle Θ of arbitrary expectation values involving the unitary operation can, in the general case, be evaluated by four expectation values obtained from replacing the corresponding unitary with fermionic shift operations (II). Fermionic shift operations can be constructed through the original unitary and unitary operations generated by the nullspace projector P0 of the fermionic excitation generator. Other operators and generators are disclosed.

    CRYPTOGRAPHIC PROCESSOR FOR FULLY HOMOMORPHIC ENCRYPTION (FHE) APPLICATIONS

    公开(公告)号:US20240235810A1

    公开(公告)日:2024-07-11

    申请号:US18388687

    申请日:2023-11-10

    CPC classification number: H04L9/008 H04L9/0618

    Abstract: Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic operation. The first cryptographic processing module includes first input circuitry to receive ciphertext input symbols. A first pipeline stage performs a first operation on the ciphertext input symbols and generates a first stage output. On-chip memory temporarily stores the first stage output and feeds the first stage output to a second pipeline stage in a pipelined manner. The second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage.

    METHODS AND MODULES FOR ACCELERATING INFERENCE VIA DISTRIBUTED DEVICES

    公开(公告)号:US20240220829A1

    公开(公告)日:2024-07-04

    申请号:US18087897

    申请日:2022-12-23

    CPC classification number: G06N5/04

    Abstract: Methods and modules for accelerating inference computations in transformer models using edge devices includes partitioning inputs for each layer and synchronizing between transformer layers. A method includes receiving a transformer input, partitioning the transformer input into two or more first-stage divisions, processing each first-stage division into a processed first-stage division, and combining the processed first-stage divisions into a first output. A module includes a computing device for partitioning a transformer input into two or more divisions, transmitting each of the divisions, and receiving processed divisions, as well as two or more transformer processing units, each for receiving a division from the computing device, processing the division into a processed division, and sending the processed division to the computing device.

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