公开(公告)号：US20230328964A1

公开(公告)日：2023-10-12

申请号：US18089956

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng Lee ,  Sangwoo Pae ,  Namhyun Lee

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor device includes a first fin pattern protruding from a substrate and extending in a first direction; first and second active layers extending in the first direction on the first fin pattern, the second active layer being at a level higher than a level of the first active layer, the first and second active layers forming a first active layer structure; a first gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, and extending in a second direction; and a second gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, extending in the second direction, and disposed to be parallel to the first gate. The first active layer includes a first region extending from a first overlapping region of the first active layer overlapping the first gate by a first length in a direction away from the second gate, and the second active layer includes a first region extending from a first overlapping region of the second active layer overlapping the first gate by a second length in a direction away from the second gate, the second length shorter than the first length.

公开(公告)号：US11735491B2

公开(公告)日：2023-08-22

申请号：US17505953

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunggyun Noh ,  Gun-Hee Bae ,  Sangwoo Pae ,  Jinsoo Bae ,  Deok-Seon Choi ,  Il-Joo Choi

IPC: H01L23/367 ,  H01L23/40 ,  H01L23/22

CPC classification number: H01L23/367 ,  H01L23/22 ,  H01L23/4012 ,  H01L2023/4087

Abstract: A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

公开(公告)号：US11961824B2

公开(公告)日：2024-04-16

申请号：US17680877

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunggyun Noh ,  Sangwoo Pae ,  Jinsoo Bae ,  Iljoo Choi ,  Deokseon Choi ,  Keunho Rhew

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/14 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/13018 ,  H01L2224/1412 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/3512

Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

公开(公告)号：US11239162B2

公开(公告)日：2022-02-01

申请号：US16877945

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miji Lee ,  Taeyoung Jeong ,  Yoonkyeong Jo ,  Sangwoo Pae ,  Hwasung Rhee

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US11637065B2

公开(公告)日：2023-04-25

申请号：US17648829

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miji Lee ,  Taeyoung Jeong ,  Yoonkyeong Jo ,  Sangwoo Pae ,  Hwasung Rhee

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US10048137B2

公开(公告)日：2018-08-14

申请号：US14506956

申请日：2014-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongtaek Lee ,  Sangwoo Pae ,  Junekyun Park

IPC: G01K7/00 ,  G01K7/01 ,  H01L29/78 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L27/088 ,  H01L23/34

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of conductive lines formed on the semiconductor substrate; and an electrode for temperature measurement. The electrode is connected to the plurality of conductive lines. An electronic device includes a semiconductor device and has a temperature sensing function. The semiconductor device includes: a semiconductor substrate; a plurality of conductive lines formed on the semiconductor substrate; and an electrode for temperature measurement.