公开(公告)号：US12040401B2

公开(公告)日：2024-07-16

申请号：US17994565

申请日：2022-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Joohee Jung ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US20240321875A1

公开(公告)日：2024-09-26

申请号：US18603591

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok PARK ,  Jaeho Jeon ,  Donghoon Hwang ,  Taehyun Ryu ,  Namhyun Lee

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a plurality of nanosheet stacks on the active region, a plurality of gate lines extending in a second horizontal direction intersecting the first horizontal direction, on the active region, and surrounding the plurality of nanosheet stacks, and a first insulating pattern between two nanosheet stacks adjacent in the first horizontal direction among the plurality of nanosheet stacks, on the active region, and extending in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, wherein the first insulating pattern is in contact with the plurality of nanosheet stacks.

公开(公告)号：US20230328964A1

公开(公告)日：2023-10-12

申请号：US18089956

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng Lee ,  Sangwoo Pae ,  Namhyun Lee

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor device includes a first fin pattern protruding from a substrate and extending in a first direction; first and second active layers extending in the first direction on the first fin pattern, the second active layer being at a level higher than a level of the first active layer, the first and second active layers forming a first active layer structure; a first gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, and extending in a second direction; and a second gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, extending in the second direction, and disposed to be parallel to the first gate. The first active layer includes a first region extending from a first overlapping region of the first active layer overlapping the first gate by a first length in a direction away from the second gate, and the second active layer includes a first region extending from a first overlapping region of the second active layer overlapping the first gate by a second length in a direction away from the second gate, the second length shorter than the first length.

公开(公告)号：US12107172B2

公开(公告)日：2024-10-01

申请号：US18478410

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Taeyong Kwon ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

公开(公告)号：US11515421B2

公开(公告)日：2022-11-29

申请号：US17205282

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Joohee Jung ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US20230422479A1

公开(公告)日：2023-12-28

申请号：US18133964

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.

公开(公告)号：US20230402458A1

公开(公告)日：2023-12-14

申请号：US18196191

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong Joe ,  Hyohoon Byeon ,  Namhyun Lee ,  Sungkeun Lim ,  Yuyeong Jo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66439 ,  H01L29/66545

Abstract: A semiconductor device includes a first transistor structure on a substrate, the first transistor structure including first channel layers spaced apart from each other, a first gate electrode surrounding the first channel layers, a first source/drain region connected to the first channel layers on a first side of the first gate electrode, and a second source/drain region connected to the first channel layers on a second side of the first gate electrode that is opposite to the first side of the first gate electrode, and a second transistor structure on the first transistor structure, the second transistor structure including second channel layers spaced apart from each other, a second gate electrode surrounding the second channel layers, and a third source/drain region connected to the second channel layers on a first side of the second gate electrode.

公开(公告)号：US11799036B2

公开(公告)日：2023-10-24

申请号：US17370464

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Taeyong Kwon ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.