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    Memory device having low write error rate
    1.
    发明授权
    Memory device having low write error rate 有权

    公开(公告)号：US11869575B2

    公开(公告)日：2024-01-09

    申请号：US17563619

    申请日：2021-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hoon Jung

    IPC: G11C11/40 ,  G11C11/408 ,  G11C11/409 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C11/4085 ,  G11C11/409 ,  G11C11/4087 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/222

    Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

    Magnetic junction memory device and writing method thereof
    2.
    发明授权
    Magnetic junction memory device and writing method thereof 有权

    公开(公告)号：US11443791B2

    公开(公告)日：2022-09-13

    申请号：US16848140

    申请日：2020-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Kyung Kim ,  Ji Yean Kim ,  Hyun Taek Jung ,  Ji Eun Kim ,  Tae Seong Kim ,  Sang-Hoon Jung ,  Jae Wook Joo

    IPC: G11C11/16

    Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

    Magnetic junction memory device and writing method thereof
    4.
    发明授权
    Magnetic junction memory device and writing method thereof 有权

    公开(公告)号：US12014763B2

    公开(公告)日：2024-06-18

    申请号：US17882790

    申请日：2022-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Kyung Kim ,  Ji Yean Kim ,  Hyun Taek Jung ,  Ji Eun Kim ,  Tae Seong Kim ,  Sang-Hoon Jung ,  Jae Wook Joo

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

    Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

    Memory device having low write error rate
    5.
    发明授权
    Memory device having low write error rate 有权

    公开(公告)号：US11238918B2

    公开(公告)日：2022-02-01

    申请号：US16691127

    申请日：2019-11-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hoon Jung

    IPC: G11C8/00 ,  G11C11/408 ,  G11C11/409 ,  G11C7/22 ,  G11C7/10

    Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

    Memory device
    6.
    发明授权
    Memory device 有权

    公开(公告)号：US10854262B2

    公开(公告)日：2020-12-01

    申请号：US16547027

    申请日：2019-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Jung

    IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H03K19/20

    Abstract: A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.

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