公开(公告)号：US20240282573A1

公开(公告)日：2024-08-22

申请号：US18512923

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehee Jung ,  Seik Jang ,  Jaeseok Kim ,  Hyungkyu Kim ,  Seungjin Baek ,  Changsun Yeo ,  Kwangjin Yoo ,  Jinhwan Jeong ,  Hyeonjeong Jung ,  Wonchul Choi

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/458 ,  C23C16/50 ,  H01J37/32 ,  H01L21/3213

CPC classification number: H01L21/0228 ,  C23C16/042 ,  C23C16/402 ,  C23C16/4583 ,  C23C16/50 ,  H01J37/32449 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/32139 ,  H01J2237/332

Abstract: A method for processing a substrate including: loading a plurality of first substrates and a plurality of second substrates on which mask patterns are formed into a process chamber; supplying a first pretreatment gas into the process chamber; surface processing the plurality of first substrates using first plasma generated from the first pretreatment gas; supplying a second pretreatment gas into the process chamber; surface processing the plurality of first substrates and the plurality of second substrates using second plasma generated from the second pretreatment gas; supplying precursors to be adsorbed onto each of the plurality of first substrates and the plurality of second substrates into the process chamber; supplying a reactive gas into the process chamber; and depositing a thin film covering the mask patterns on each of the plurality of first substrates and the plurality of second substrates using third plasma generated from the reactive gas and the precursors.

公开(公告)号：US20200211938A1

公开(公告)日：2020-07-02

申请号：US16593300

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongchan PARK ,  Sanghyun Kwon ,  Hyungkyu Kim ,  Han Kim ,  Choonkeun Lee ,  Seungon Kang

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/31 ,  H01L23/498 ,  H01L23/373 ,  H01L23/367

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, a heat-dissipating member, including graphite, which is disposed on the inactive surface of the semiconductor chip; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member, and a connection structure, which includes a redistribution layer electrically connected to the connection pad, disposed on the active surface of the semiconductor chip, and at least a side surface of the heat-dissipating member is coplanar with a side surface of the semiconductor chip.

公开(公告)号：US10438685B2

公开(公告)日：2019-10-08

申请号：US15991733

申请日：2018-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungkyu Kim ,  Sang-Hoon Jung

IPC: G11C29/00 ,  G11C16/08 ,  G11C17/16 ,  G11C29/20 ,  G11C29/44

Abstract: A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.

公开(公告)号：US11901269B2

公开(公告)日：2024-02-13

申请号：US17687072

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongchan Park ,  Sanghyun Kwon ,  Hyungkyu Kim ,  Han Kim ,  Choonkeun Lee ,  Seungon Kang

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/433 ,  H01L23/31 ,  H01L23/498 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L23/49568 ,  H01L23/3178 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49805 ,  H01L23/49827 ,  H01L2224/02371

Abstract: A semiconductor package includes: a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface opposite to the active surface; a heat-dissipating member disposed on the inactive surface of the semiconductor chip and including graphite; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member; a capping metal layer disposed directly between the heat-dissipating member and the encapsulant; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the heat-dissipating member includes holes passing through at least a portion of the heat-dissipating member, and the holes overlap the inactive surface of the semiconductor chip.