公开(公告)号：US10685837B2

公开(公告)日：2020-06-16

申请号：US16240216

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ik Oh ,  Daehyun Jang ,  Ha-Na Kim ,  Kyoungsub Shin

IPC: H01L21/027 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11556 ,  H01L27/24 ,  H01L25/065 ,  H01L25/00 ,  H01L27/11521 ,  H01L45/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US10236442B2

公开(公告)日：2019-03-19

申请号：US15227334

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Seo ,  Jong-Kyu Kim ,  Jung-Ik Oh ,  Inho Kim ,  Jongchul Park ,  Gwang-Hyun Baek ,  Hyun-woo Yang

IPC: H01L43/12 ,  H01L21/3213 ,  H01L21/02 ,  H01L27/22

Abstract: Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.

公开(公告)号：US09941122B2

公开(公告)日：2018-04-10

申请号：US15249903

申请日：2016-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ik Oh ,  Daehyun Jang ,  Ha-Na Kim ,  Kyoungsub Shin

IPC: H01L25/00 ,  H01L27/11 ,  H01L45/00 ,  H01L21/027 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11556 ,  H01L27/24 ,  H01L25/065 ,  H01L27/11521

CPC classification number: H01L21/0274 ,  H01L21/30604 ,  H01L21/3085 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US09876165B2

公开(公告)日：2018-01-23

申请号：US15180843

申请日：2016-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kuk Kim ,  Jong-Kyu Kim ,  Jongchul Park ,  Inho Kim ,  Gwang-Hyun Baek ,  Jung-Ik Oh

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.

公开(公告)号：US20170110656A1

公开(公告)日：2017-04-20

申请号：US15227334

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Seo ,  Jong-Kyu Kim ,  Jung-Ik Oh ,  Inho Kim ,  Jongchul Park ,  Gwang-Hyun Baek ,  Hyun-woo Yang

IPC: H01L43/12 ,  H01L43/08 ,  H01L21/768 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L21/02071 ,  H01L21/32138 ,  H01L27/222

Abstract: Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.

公开(公告)号：US10211053B2

公开(公告)日：2019-02-19

申请号：US15910583

申请日：2018-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ik Oh ,  Daehyun Jang ,  Ha-Na Kim ,  Kyoungsub Shin

IPC: H01L21/027 ,  H01L27/11556 ,  H01L21/306 ,  H01L27/24 ,  H01L21/308 ,  H01L27/11582 ,  H01L27/11575 ,  H01L45/00 ,  H01L27/11521 ,  H01L25/00 ,  H01L25/065

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US10199566B2

公开(公告)日：2019-02-05

申请号：US15220719

申请日：2016-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ik Oh ,  Jong-Kyu Kim ,  Jongchul Park ,  Gwang-Hyun Baek ,  Kyungrae Byun ,  Hyun-Woo Yang

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.

公开(公告)号：US20140057429A1

公开(公告)日：2014-02-27

申请号：US13910734

申请日：2013-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-soo Lee ,  Han-Na Cho

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Abstract translation: 形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。 第一光致抗蚀剂图案形成在堆叠结构上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。 钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。 通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。 可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。