公开(公告)号：US20240321873A1

公开(公告)日：2024-09-26

申请号：US18429611

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Juneyoung PARK ,  Jaeran JANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5226

Abstract: An integrated circuit device, including a substrate having a plurality of device regions extending in a first horizontal direction, a plurality of gate electrodes on the plurality of device regions extending in a second horizontal direction that is orthogonal to the first horizontal direction, a plurality of source/drain regions between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes, the plurality of source/drain regions being on portions of the plurality of device regions, a plurality of gate cut regions cutting the plurality of gate electrodes and extending in the first horizontal direction, and a plurality of contact structures including a plurality of contact body portions and a plurality of contact finger portions, the plurality of contact body portions filling the plurality of gate cut regions and extending in the first horizontal direction.

公开(公告)号：US20230231023A1

公开(公告)日：2023-07-20

申请号：US18085331

申请日：2022-12-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate, active regions extending in a first horizontal direction on the substrate, and including first and second active regions spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and third and fourth active regions spaced apart from each other in the second horizontal direction, first to fourth source/drain regions on the first to fourth active regions, first to fourth contact plugs connected to the first to fourth source/drain regions, a first isolation insulating pattern disposed between the first and second contact plugs, and a second isolation insulating pattern disposed between the third and fourth contact plugs, wherein a first length of the first isolation insulating pattern is smaller than a second length of the second isolation insulating pattern in a vertical direction.

公开(公告)号：US20240371731A1

公开(公告)日：2024-11-07

申请号：US18507549

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin SHIN ,  Heonjong SHIN ,  June Young PARK ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a support member, an active region, source and drain regions, and a gate electrode. The support member may include a substrate insulation layer including separating insulators and a power wire disposed at a space between the separating insulators. The active region may be disposed on the power wire. The source and drain regions may be positioned adjacent to the active region. The gate electrode may be disposed on the active region.

公开(公告)号：US20240321689A1

公开(公告)日：2024-09-26

申请号：US18441327

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juneyoung PARK ,  Heonjong SHIN ,  Jongmin SHIN ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including an active device layer including a plurality of source/drain patterns, a plurality of insulating layers on the active device layer, a back end of line (BEOL) structure on the plurality of insulating layers and configured to supply electric power to the active device layer, an intermediate layer between the plurality of insulating layers and the BEOL structure, and at least one power via penetrating through the intermediate layer and at least a part in each of the plurality of insulating layers in a vertical direction. The at least one power via electrically connects the BEOL structure and the active device layer. At least a part of a side surface of the at least one power via is in contact with the intermediate layer.

公开(公告)号：US20230223451A1

公开(公告)日：2023-07-13

申请号：US18073682

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

公开(公告)号：US20180130796A1

公开(公告)日：2018-05-10

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan JUN ,  Deokhan BAE ,  HeonJong SHIN ,  Jaeran JANG ,  Moon Gi CHO ,  YoungWoo CHO

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.