公开(公告)号：US20200219808A1

公开(公告)日：2020-07-09

申请号：US16441042

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Gyu HWANG ,  Kyoung Woo LEE ,  YoungWoo CHO ,  IL SUP KIM ,  Su Hyun BARK ,  Young-Ju PARK ,  Jong Min BAEK ,  Min HUH

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

公开(公告)号：US20180130796A1

公开(公告)日：2018-05-10

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan JUN ,  Deokhan BAE ,  HeonJong SHIN ,  Jaeran JANG ,  Moon Gi CHO ,  YoungWoo CHO

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.