知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.025 seconds)

    Motor and washing machine having the same
    1.
    发明授权
    Motor and washing machine having the same 有权

    公开(公告)号：US11374475B2

    公开(公告)日：2022-06-28

    申请号：US16819286

    申请日：2020-03-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinki Lee ,  Jaejun Lee ,  Minseong Im ,  Sukwon Jeong

    IPC: H02K29/03 ,  H02K1/2786 ,  H02K21/22 ,  D06F23/04 ,  D06F37/40 ,  D06F37/30

    Abstract: A motor of the invention includes a stator having a slot wound with a coil and a circular shaped housing accommodating the stator, and a rotor disposed on an inner surface of the housing and spaced apart from the slot and having a plurality of permanent magnets having the same number as magnetic poles and having different magnetic polarities. Each of the plurality of permanent magnets has a length corresponding to a first angle according to the number of magnetic poles. The plurality of permanent magnets are spaced apart from each other at a third angle according to the first angle and a second angle corresponding to the number of magnetic poles. The first, second, third angles of the motor refer to a center point of the housing as an angle reference point. The motor of an embodiment may be a motor provided in a washing machine.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250118651A1

    公开(公告)日：2025-04-10

    申请号：US18733206

    申请日：2024-06-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungryong OH ,  Jaejun Lee ,  Junho Lee

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

    Abstract: A semiconductor package includes a first semiconductor chip including a semiconductor substrate having an active surface and an inactive surface, a device layer on the active surface, first chip pads on the device layer, and a first through-electrode and a second through-electrode, where the first through-electrode and the second through-electrode penetrate the semiconductor substrate, at least one of the first chip pads is connected to the first through-electrode and at least one of the first chip pads is connected to the second through-electrode, a redistribution structure including a redistribution layer on the inactive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer, contact pads on an upper surface of the redistribution structure, and a second semiconductor chip on the redistribution structure and including second chip pads connected to the contact pads.

    Semiconductor memory device with operation limit controller
    4.
    发明授权
    Semiconductor memory device with operation limit controller 有权

    公开(公告)号：US12040043B2

    公开(公告)日：2024-07-16

    申请号：US17720843

    申请日：2022-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonghoon Joo ,  Jaejun Lee ,  Ilhan Choi

    IPC: G11C11/06 ,  G06F1/20 ,  G11C7/04

    CPC classification number: G11C7/04 ,  G06F1/206 ,  G11C2207/2227

    Abstract: A semiconductor memory device includes a plurality of input-output pins configured to communicate with a memory controller, a command control logic, a temperature measurement circuit and an operation limit controller. The command control logic controls an operation of the semiconductor memory device based on command signals and control signals transferred from the memory controller through control pins among the plurality of input-output pins. The temperature measurement circuit measures an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature. The operation limit controller, when it is determined based on the temperature code that the operation temperature exceeds a risk temperature, controls an internal operation of the semiconductor memory device regardless of the command signals and the control signals transferred from the memory controller to thereby decrease a power consumption of the semiconductor memory device.

    Memory module and on-die termination setting method thereof
    5.
    发明授权
    Memory module and on-die termination setting method thereof 有权
    存储器模块和片上终端设置方法

    公开(公告)号：US08929119B2

    公开(公告)日：2015-01-06

    申请号：US13772895

    申请日：2013-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaejun Lee ,  Bo-Ra Kim ,  Jeonghoon Baek

    IPC: G11C13/00 ,  G11C5/06 ,  G11C7/10

    CPC classification number: G11C5/06 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.

    Abstract translation: 存储器系统包括在印刷电路板上的多个存储器件，每个存储器件包括多个外部焊盘; 形成在印刷电路板上的多个连接端子，并且电连接到相应的外部焊盘; 以及形成在印刷电路板上以将连接端子与外部焊盘连接的多条信号线，每条信号线在对应的连接端子和对应的外部焊盘之间并具有一定的长度。 多个存储器件布置在与多个连接端子不同的距离处，并且将连接端子与存储器件的外部焊盘连接的每个信号线都连接到或不连接短截止电阻器，这取决于长度 线。

    Apparatus, memory device, and method for multi-phase clock training
    6.
    发明授权
    Apparatus, memory device, and method for multi-phase clock training 有权

    公开(公告)号：US12198783B2

    公开(公告)日：2025-01-14

    申请号：US17959663

    申请日：2022-10-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegook Kim ,  Woojin Na ,  Taegeun Yoo ,  Hyeseung Yu ,  Jaejun Lee

    IPC: G11C7/22 ,  G11C7/10

    Abstract: Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.

Patent Agency Ranking