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公开(公告)号：US08929119B2
公开(公告)日：2015-01-06
申请号：US13772895
申请日：2013-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaejun Lee , Bo-Ra Kim , Jeonghoon Baek
CPC classification number: G11C5/06 , G11C7/1045 , G11C7/1057 , G11C7/1084
Abstract: A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.
Abstract translation: 存储器系统包括在印刷电路板上的多个存储器件，每个存储器件包括多个外部焊盘; 形成在印刷电路板上的多个连接端子，并且电连接到相应的外部焊盘; 以及形成在印刷电路板上以将连接端子与外部焊盘连接的多条信号线，每条信号线在对应的连接端子和对应的外部焊盘之间并具有一定的长度。 多个存储器件布置在与多个连接端子不同的距离处，并且将连接端子与存储器件的外部焊盘连接的每个信号线都连接到或不连接短截止电阻器，这取决于长度 线。
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Patent Agency Ranking
公开(公告)号：US11477880B2
公开(公告)日：2022-10-18
申请号：US17337850
申请日：2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号：US11785710B2
公开(公告)日：2023-10-10
申请号：US17947397
申请日：2022-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号：US20130223123A1
公开(公告)日：2013-08-29
申请号：US13772895
申请日：2013-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaejun Lee , Bo-Ra Kim , Jeonghoon Baek
IPC: G11C5/06
CPC classification number: G11C5/06 , G11C7/1045 , G11C7/1057 , G11C7/1084
Abstract: A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.
Abstract translation: 存储器系统包括在印刷电路板上的多个存储器件，每个存储器件包括多个外部焊盘; 形成在印刷电路板上的多个连接端子，并且电连接到相应的外部焊盘; 以及形成在印刷电路板上以将连接端子与外部焊盘连接的多条信号线，每条信号线在对应的连接端子和对应的外部焊盘之间并具有一定的长度。 多个存储器件布置在与多个连接端子不同的距离处，并且将连接端子与存储器件的外部焊盘连接的每个信号线都连接到或不连接短截止电阻器，这取决于长度 线。
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公开(公告)号：US12063736B2
公开(公告)日：2024-08-13
申请号：US18240619
申请日：2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号：US20230413424A1
公开(公告)日：2023-12-21
申请号：US18240619
申请日：2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonseop LEE , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , H01L25/112 , H01L25/0657 , H05K1/025 , G11C5/063 , G11C8/18 , G06F13/4086 , G11C5/04 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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