知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.02 seconds)

    GATE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    1.
    发明申请
    GATE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250040124A1

    公开(公告)日：2025-01-30

    申请号：US18442274

    申请日：2024-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Kong ,  Sungho Jang ,  Junsoo Kim ,  Junbum Lee ,  Jaehyun Choi ,  Ilgweon Kim ,  Jeonghoon Oh

    IPC: H10B12/00

    Abstract: A gate structure includes a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12213302B2

    公开(公告)日：2025-01-28

    申请号：US17725069

    申请日：2022-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Jaeho Hong

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

    Methods of Fabricating Semiconductor Devices
    5.
    发明申请
    Methods of Fabricating Semiconductor Devices 有权
    制造半导体器件的方法

    公开(公告)号：US20160181258A1

    公开(公告)日：2016-06-23

    申请号：US14976536

    申请日：2015-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HyeoungWon Seo ,  Daehyun Moon ,  Jooyoung Lee ,  Ilgweon Kim ,  Dongjin Jung

    IPC: H01L27/11 ,  H01L21/265 ,  H01L29/423 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/4236 ,  H01L21/26513 ,  H01L21/762 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0696 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66734

    Abstract: Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.

    Abstract translation: 制造半导体器件的方法包括：在衬底中通过将第一导电类型的第一杂质从衬底的顶表面的单元区域和外围区域中注入到第一目标深度来形成第一杂质区; 通过将第一导电类型的第二杂质注入到所述电池区域和所述周边区域中而形成到所述电池区域和所述周边区域中的第二杂质区域到比所述衬底的所述顶表面的所述第一深度小的第二靶材深度 ; 在所述单元区域中形成具有沟道的单元晶体管，其中所述第一杂质区域形成所述单元晶体管的沟道; 以及在所述周边区域中形成具有沟道的外围晶体管，其中所述第二杂质区域形成所述外围晶体管的沟道。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240224494A1

    公开(公告)日：2024-07-04

    申请号：US18414893

    申请日：2024-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11917805B2

    公开(公告)日：2024-02-27

    申请号：US17541584

    申请日：2021-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    Semiconductor memory devices
    9.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11887648B2

    公开(公告)日：2024-01-30

    申请号：US17362138

    申请日：2021-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

    IPC: H01L29/66 ,  G11C11/39 ,  G11C11/402 ,  H01L29/749 ,  H01L27/102

    CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

    Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

    Integrated circuit devices
    10.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

Patent Agency Ranking