公开(公告)号：US09825142B2

公开(公告)日：2017-11-21

申请号：US14976536

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HyeoungWon Seo ,  Daehyun Moon ,  Jooyoung Lee ,  Ilgweon Kim ,  Dongjin Jung

IPC: H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108

CPC classification number: H01L29/4236 ,  H01L21/26513 ,  H01L21/762 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0696 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66734

Abstract: Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.

公开(公告)号：US09865453B2

公开(公告)日：2018-01-09

申请号：US15191581

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehyun Moon ,  HyeoungWon Seo ,  Ilgweon Kim ,  Jooyoung Lee ,  Dongjin Jung

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/02 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L21/02164 ,  H01L21/02238 ,  H01L21/0228 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10897 ,  H01L29/0649

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of recess regions on an upper surface of a substrate, forming a first oxide layer in the recess regions, forming a polysilicon layer on the first oxide layer, forming a second oxide layer by oxidizing the polysilicon layer, and forming a gap-fill layer on the second oxide layer to fill the recess regions, wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer.

公开(公告)号：US20160181258A1

公开(公告)日：2016-06-23

申请号：US14976536

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HyeoungWon Seo ,  Daehyun Moon ,  Jooyoung Lee ,  Ilgweon Kim ,  Dongjin Jung

IPC: H01L27/11 ,  H01L21/265 ,  H01L29/423 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/4236 ,  H01L21/26513 ,  H01L21/762 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0696 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66734

Abstract: Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.

Abstract translation: 制造半导体器件的方法包括：在衬底中通过将第一导电类型的第一杂质从衬底的顶表面的单元区域和外围区域中注入到第一目标深度来形成第一杂质区; 通过将第一导电类型的第二杂质注入到所述电池区域和所述周边区域中而形成到所述电池区域和所述周边区域中的第二杂质区域到比所述衬底的所述顶表面的所述第一深度小的第二靶材深度 ; 在所述单元区域中形成具有沟道的单元晶体管，其中所述第一杂质区域形成所述单元晶体管的沟道; 以及在所述周边区域中形成具有沟道的外围晶体管，其中所述第二杂质区域形成所述外围晶体管的沟道。