公开(公告)号：US20250040124A1

公开(公告)日：2025-01-30

申请号：US18442274

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsik Kong ,  Sungho Jang ,  Junsoo Kim ,  Junbum Lee ,  Jaehyun Choi ,  Ilgweon Kim ,  Jeonghoon Oh

IPC: H10B12/00

Abstract: A gate structure includes a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.

公开(公告)号：US09842841B2

公开(公告)日：2017-12-12

申请号：US14849651

申请日：2015-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hun Kim ,  Ilgweon Kim ,  Junhwa Song ,  Jeonghoon Oh ,  WonSeok Yoo ,  Eun-Sun Lee

IPC: H01L21/8242 ,  H01L21/762 ,  H01L21/311 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/8238 ,  H01L49/02

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10891 ,  H01L28/91

Abstract: A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.

公开(公告)号：US20250151265A1

公开(公告)日：2025-05-08

申请号：US18740568

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongman Park ,  Sungho Jang ,  Seungho Hong ,  Jeonghoon Oh

IPC: H10B12/00

Abstract: An integrated circuit device includes gate structures arranged on an upper surface of a substrate, a first impurity region arranged at the upper surface of the substrate, wherein the first impurity region is adjacent to a first gate structure of the gate structures, a first contact pad arranged on the upper surface of the substrate, wherein the first contact pad comprises a recess recessed in a vertical direction perpendicular to the upper surface of the substrate from an upper surface of the first contact pad toward the upper surface of the substrate, a metal silicide layer disposed in the recess, and a contact via connected to the metal silicide layer and extending in the vertical direction. A lower end of the contact via is disposed in the recess and connected to the metal silicide layer. The contact via is spaced apart from the substrate in the vertical direction.

公开(公告)号：US09837423B2

公开(公告)日：2017-12-05

申请号：US14967765

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghoon Oh ,  Ilgweon Kim ,  Hyon Namkung

IPC: H01L29/10 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10814 ,  H01L27/10876

Abstract: A device isolation region is formed, delimiting an active region in a substrate. A word line is formed, extending across the active region and the device isolation region and buried therein. A bit line is formed crossing the word line on the substrate. A channel is formed adjacent the word line, the channel having a retrograde doping profile having a doping concentration that increases away from a top surface of the active region. Formation of the channel includes performing a field ion implantation in the active region having a projected range near a bottom of the device isolation region.

公开(公告)号：US09484409B2

公开(公告)日：2016-11-01

申请号：US14846176

申请日：2015-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Sun Lee ,  Junhwa Song ,  Ji Hun Kim ,  Jeonghoon Oh

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L27/11 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/412

CPC classification number: H01L29/1033 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1079

Abstract: A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device.

Abstract translation: 一种半导体器件包括：半导体衬底，包括具有第一导电类型的阱掺杂剂层，阱掺杂剂层上的栅极电极，阱掺杂剂层中的沟道掺杂剂层，并且与半导体衬底的顶表面间隔开;沟道 栅电极和沟道掺杂剂层之间的区域以及栅电极两侧的阱掺杂剂层中的源/漏区。 沟道掺杂剂层和沟道区具有第一导电类型。 源极/漏极区域具有第二导电类型。 在沟道掺杂剂层中具有第一导电类型的掺杂剂的浓度高于沟道区中具有第一导电类型的掺杂剂的浓度。 半导体器件可以用在存储器件的读出放大器中。